Gabe's Commentary: Verilog, SystemVerilog, or both

Four years ago, as the semiconductor industry process technology crossed below 193 nanometers, the number of transistors available to a design team made it necessary to explore new design methods at a level of abstraction above register transfer level (RTL). The industry had embraced Verilog for over a decade by then, and only then did it realize that the language was running out of capabilities for engineers needing to describe a design at levels more abstract than RTL.

The first EDA vendor to notice the Verilog deficiency was Synopsys, a company that had tried without success to build a competitive VHDL simulator for over ten years. Because of this competitive history, it was impossible for Synopsys to credibly suggest that a mixed language methodology using behavioral VHDL and RTL Verilog might provide a feasible solution. So, Synopsys engineering was tasked with developing a new solution in the shortest possible amount of time. The result was Synposys' SystemC.

Today OSCI (Open SystemC Initiative) gives the language the aura of an open source product, and SystemC has found a number of users, mostly in Japan and in Europe. Cadence, CoWare, and Forte Design Systems are the major providers of SystemC products, although Mentor, a company that likes to take an ecumenical approach to the EDA market, does provide some SystemC tools, and Synopsys of course supports SystemC simulation. But it has been obvious since its introduction that the language has limitations and cannot play at the system level the same role that Verilog plays at the RT level.

The Verilog camp, and in particular the 1364 Working Group of the DASC (Design Automation Standard Committee) of the Computer Society of the IEEE, has been busy extending the Verilog language using VHDL as the blueprint to provide some of the facilities that SystemC has. This version is referred to as Verilog 2005.  By the time they are finished Verilog will be more complex to use than VHDL ever was.

Synopsys is not a company that fails twice (VHDL is the only exception). It quickly learned that SystemC was a temporary band-aid and thus acquired Co-Design, a British company that had developed a new language called Superlog. Superlog is the legitimate extension of Verilog, only redesigned, not patched up. For reasons that only Synopsys marketing wizards can even verbalize (notice I did not say explain), the language was renamed SystemVerilog and donated to the most efficient standard development organization in the EDA space, Accellera, for the purpose of making it an industry standard.

Warning bells went off all over the Verilog camp. Here was a language that could coexist with present Verilog and could take seats away from the Verilog installed base. Of course this fact was just fine with Synopsys, and even Mentor was not exceptionally disturbed at the prospect, since their simulation environment is truly language neutral. The Cadence people still believe that Verilog and SystemC are sufficient and that a new language, even if complementary, could allow their two major competitors to capture some of their accounts.

Enter, or better yet, re-enter Victor Berman, as Cadence's Group Director for Language Standards. Victor had been at Cadence during the Verilog heydays, and before that, he had helped to design VHDL. So Victor is now the Verilog Champion who can also be the SystemC apologist given his expertise in discussing anything that has to do with simulation languages. Victor’s task is to slow down the industry acceptance of SystemVerilog while Cadence’s engineering group develops the equivalent capabilities for the company's simulation platform.

But those pestering folks at Accellera just do not know how to mess up a standard development and so SystemVerilog is now available well before Verilog 2005 has even figured out who will develop tools based on the new proposed language. The 1364 committee first tried to strong arm Accellera by demanding that SystemVerilog, which at the time was not finished, be turned over to them for "incorporation into Verilog". Fortunately there are people that use their brains in Accellera and the request was politely but firmly denied. So now the 1364 committee is resorting to religion, proclaiming to all that will listen that there is only one Verilog, it is Verilog, and that SystemVerilog is a false prophet.

The 1364 Working Group is looking in the wrong direction. Instead of trying to extend Verilog into behavioral constructs, they should make sure that they provide Verilog with the capabilities the language needs to deal with verification problems encountered below the RTL level. Such a language could co-exist with a behavioral language that also provides support for assertions and testbenches, such as SystemVerilog. The two languages share many syntax and semantics primitives, so the designers have a powerful tool that can be used from architectural design to layout. But engineers working at the gate level would not have to carry the overhead of the behavioral constructs, and vice versa.

Thus the combination of SystemVerilog and Verilog is what designers really need. Cadence has shown that a multi-language platform is the correct solution to the verification problem. Both Mentor and Synopsys also have multi-language solutions. The stubbornness of the DASC 1364 Working Group is not only difficult to understand, it is anachronistic as well. The 1364 Working Group is desperately holding on an old idea that has been proven unworkable by the VHDL experiment.

The present battle is being fought in the IEEE. On one corner you have Accellera with SystemVerilog, a capable language supported by usable tools, and on the other you have Verilog 2005, a promised language with no tools. The DASC follows the five years standard development process common to the IEEE and is looking at 2005 as the next available window for releasing a standard. This process is well-suited to established, slow changing industries, but, as any one associated with the semiconductor industry knows, if you take five years to develop a tool you are two process nodes too late in EDA.

Accellera has joined the Corporate Society of the IEEE, with Synopsys and Mentor, and can develop a working group under this umbrella to make SystemVerilog an IEEE standard much faster than the DASC 1364 can get its new version of Verilog developed. The DASC still does not know how much it would take to incorporate the SystemVerilog capabilities into its Verilog project, but it is the only weapon in the IEEE available to Cadence to defend its marketing stance and to Verisity and Magma to slow down the process and give them an opportunity to catch up. To be sure, Cadence has a strong position. Victor Berman is the Vice Chair of the DASC and also sits on the Accellera board, so he can generate a reasonable amount of discomfort.

Yesterday the IEEE Corporate Advisory Group agreed to sponsor the PAR (Project Authorization Request) for SystemVerilog. I hope that the DASC will see the wisdom of this decision and work toward improving Verilog in a more helpful direction for engineers designing large systems on chip.