News and New Products

Core stresses performance and power

By Robert Cravotta -- EDN, 6/24/2004

Tensilica’s Xtensa LX processor core drives down power consumption and increases computational and throughout performance. The Xtensa LX core incorporates fine-grained clock gating for every functional element, including user-defined extensions. This level of clock gating helps reduce the core’s power dissipation by 25% over the base Xtensa V core configuration.

The Xtensa LX core is the first implementation of the FLIX (flexible-length instruction extensions) architecture that supports modeless intermixing of 16-, 24, 32-, or 64-bit instructions and better balances the performance and code-versus-size trade-offs when using a fixed-sized-instruction-length architecture. The FLIX architecture adds approximately 2000 gates of control logic to the core and supports multiple, concurrent, independent, and compound operations per instruction cycle, and it is fully compatible with the 16- and 24-bit Xtensa instruction-set architecture.

The Xtensa LX implements LX-port and -queue interfaces and supports an optional second load/store unit to potentially increase the I/O throughput by several orders of magnitude. Port connections can be arbitrarily as wide as 1024×1024 bits, and they can directly connect two Xtensa LX cores or an Xtensa LX core to external RTL. The queue interface logically operate as traditional processor registers, but the data is available without requiring a load or store before or after a computation. This approach allows queues to sustain data rates as high as one transfer per clock cycle. User-defined instruction extensions can perform multiple queue operations per cycle, including combining inputs from two input queues with local data and sending the computed values to two output queues.

You can configure the traditional five-stage pipeline with two additional pipeline stages to support memory access for instruction fetch and data load or store. This approach allows you to select the pipeline length based on the speed differences between high-clock-frequency processing coupled with large local memories or slower low-power memories. Each Xtensa LX processor configuration you create includes custom software-development tools, an instruction-set simulator, a bus-functional model, and EDA scripts.

The Xtensa LX processor will be available early this summer. You can target each processor instance to any silicon-foundry technology, and licensing is on a per-processor basis plus royalties based on the volume of processors manufactured. Licensing fees for a single processor configuration start at $550,000 for the Xtensa LX processor, and that fee includes the Vectra LX DSP engine. The Xtensa software-developers tool kit, which includes the Xtensa Xplorer development environment, Xtensa C/C++ compiler, Xtensa instruction-set simulator; and Tensilica-instruction-set compiler are priced separately.

Tensilica,1-408-986-8000, www.tensilica.com.