Synthesize optimal digital-frequency dividers

Lindo St Angel, PrairieComm Inc, Arlington Heights, IL -- EDN, 5/13/1999

For many applications, you need to divide a reference clock into one or more subclocks to use in different parts of the system. Sometimes, this divider circuit is simple. For example, a circuit that divides by an integer number is easy to construct using a few flip-flops and assorted logic gates. However, often you must build a noninteger divider, for example, a divide by 7/8 or 512/1025. In these cases, you could use a divider and a PLL to divide the input reference by the denominator and then multiply the result by the numerator, but the circuit would become relatively complex and require analog components.

However, if your application can tolerate some clock jitter, there is another answer: the binary-rate-multiplier (BRM) circuit. This well-known circuit works by multiplexing two dividers into and out of the divide path. Unfortunately, it is sometimes difficult to find the set of design parameters that gives the least amount of jitter and the desired divider ratio. Using the following method and circuit you can easily generate optimum BRMs.

The average frequency, f_OUT, of the BRM output is:

Equation 1

where f_IN is the frequency of the input reference clock, DIV₁ is the number of times the first divider divides the input clock, DIV₂ is the number of times the second divider divides the input clock, REP₁ is the number of input clock cycles for which the first divider is active, and REP₂ is the number of input clock cycles for which the second divider is active.

Instantaneous frequency of the BRM output equals the frequency of the input clock divided by the the active divider. The BRM output jitters between these two frequencies. However, you can minimize this jitter by choosing the parameters DIV₁ and DIV₂ according to

Equation 2

and

Equation 3

You then need to choose values for the parameters REP₁ and REP₂. One way to choose these values is to transform Equation 1 into an optimization problem and finding the values of REP₁ and REP₂ that minimize the transformed equation, given your chosen values for DIV₁ and DIV₂:

Equation 4

The constraints on this equation are that Z is greater than or equal to zero and that REP₁ and REP₂ are integers that are greater than or equal to unity.

You can solve Equation 4 using integer nonlinear optimization techniques. Many commercial software packages, including Microsoft Excel, solve these classes of problems. Enter Equation 4 into Excel and use the solver from the tools menu to operate on the equation, using the above constraints.

To get Z to exactly equal zero, it is important to increase the solver's precision and tolerance settings to about 10 times their default values. Also, make sure that you check your results by plugging in all values and checking that Z exactly equals zero. If it doesn't, you have to increase the solver's precision and tolerance settings.

Once you have obtained values for all the parameters, you can use them in the Verilog model to get a circuit from a logic-synthesis tool (Listing 1). If you don't have access to logic synthesis, the Verilog model can give you some idea of how to manually build up the circuit from gates. (DI #2358).