Feature

Special-purpose SRAMs smooth the ride

Data and telephone networks are experiencing more traffic of multiple types and at higher speeds with varying delivery expectations. Advanced SRAM-based memories play a big role in responding to performance and flexibility needs, and applications extend beyond the network.

By Brian Dipert, Technical Editor -- EDN, 6/24/1999

The overused description of the Internet as "the information superhighway" is both unrealistic in its expectations and too narrow in its scope. The phrase conjures up images of data rapidly flowing along a wide path that originates and ends at each computer node. Anyone who has received a file-transfer-protocol (FTP) or Web-site time-out error, heard a "circuits-are-busy" recording after dialing the modem, or suffered through slow data transfers knows the reality behind the hype.

True, today's communications network contains high-speed fiber-optic backbones, but the last-mile connection to most homes and businesses is twisted-pair wire. Most computers still access the Internet through lowly analog modems. And the computer isn't the only data portal. Televisions and telephones provide other methods of exchanging information. (However, we won't dwell on the average quality of such information exchanges.) Coaxial cable and various wireless protocols serve as alternative delivery methods.

To some extent, today's worldwide information network does resemble a roadway. The data packets are its vehicles; glass, copper, and air are its pavement.

However, any reasonably efficient roadway contains several other important components. Ramps and intersections link roadway segments with various surfaces, speed limits, and lane numbers. Stoplights and street signs bring order to what would otherwise quickly become chaotic traffic snarls, and, along with maps, direct vehicles along the fastest and shortest routes. Exchange hubs, such as train stations and ports, enable vehicles and their cargo to move among roadways and other transportation systems, such as railways and waterways.

Multiport RAMs

Content-addressable memories (CAMs) and multiport RAMs (Table 1), along with their corresponding logic engines, are the important components in the data-communications and telecommunications analogies to ramps, intersections, lights, signs, maps, and exchanges. Like FIFO buffers, multiport RAMs link data channels with different speeds, bus widths, and protocols. However, unlike FIFOs, both ports' peripherals have fully random access to any location in the memory array. This capability offers numerous benefits.

If, for example, the peripherals represent two CPUs or a CPU and DSP, the processors can decouple their activities, simultaneously accessing data in different areas of the memory and boosting overall system performance. Also, remember that the roadway system contains commuter lanes and toll ways, where travelers benefit from a reduced commuting time in exchange for the inconvenience of car-pooling or shelling out a little money.

Communications networks contain their own examples of services that favor certain travelers. Bulk file transfers, such as FTP sessions, and e-mail messages normally don't have stringent packet-to-packet latency or time-to-completion requirements. However, some customers are willing to pay a little more money for improved average service quality, even if they use the same networking equipment and access methods as their peers. Latency becomes even more critical for telephone service and for streaming multimedia traffic that runs over the data network.

Because a multiport RAM is a random-access device, one port can retrieve packets in a priority-based order that differs from the sequence in which the other port captured them. The more rigid sequential-access protocol of a FIFO buffer forces one port to access data only in the order that the other port receives it. CAMs play a corroborating role in implementing quality of service.

Cypress Semiconductor and Integrated Device Technology (IDT) are the two largest multiport-RAM suppliers. As with many other memory types, the most notable multiport-RAM advancements over the last several years have involved increased density, faster burst and sustained bandwidth, and wider buses. Both companies first use their leading-edge processes for higher volume, commodity SRAMs and later use these processors to manufacture FIFOs and multiport RAMs. This delayed transition partially explains why most of today's multiport RAMs are asynchronous-interface, 5V memories.

The rest of the picture concerns devices that multiport RAMs interact with. Many common encryption/decryption chips (for virtual-private-networking) and DSPs, such as Texas Instrument's (www.ti.com) 24-bit line, contain asynchronous buses. Asynchronous multiport RAMs offer access times as low as 12 nsec with semaphore, arbitration, and master/slave support for multiprocessor configurations. Synchronous interfaces prevail for devices in which the interfacing logic is a µP or a multicore ASIC. But with an external register and a bit of logic, you can emulate a synchronous interface on an asynchronous RAM.

Today's pipelined synchronous multiport RAMs run at 100 MHz with buses that are as much as 32 or 36 (parity) bits wide and integrated counters that simplify burst transfers. Lower latency, lower burst bandwidth, flow-through versions are also available, and some devices even allow you to select between registered and pipelined outputs within the same device on a port-by-port basis. Multiple-byte enables accommodate different-sized peripheral buses, and the ports can operate at different frequencies.

Cypress' new Flex36 devices offer a "bus-funnel" feature that integrates the buffering necessary to translate the internal X36-bit bus port to external X8/X9- or X16/X18-bit alternatives (Figure 1). Most multiport RAMs are two-port offerings, but IDT also sells 8- through 32-kbit four-port devices. IDT also offers 64- and 128-kbit serial-access memories/RAMs with a FIFOlike synchronous port on one side and a random-access asynchronous port on the other.

Historically, a surprisingly high degree of function, timing, package, and pinout compatibility existed between Cypress and IDT (see sidebar "Standardization: a mixed blessing" and Reference 1). This de facto compatibility is breaking down, however, with both vendors' latest high-density X8/X9- and X16/X18-bit offerings. Cypress uses a 100-pin TQFP for both its 5 and 3.3V versions, and IDT moves to a 128-pin TQFP for 3.3V. Pinout and package incompatibility also exists at the X36-bit bus width.

IDT claims that the larger TQFP allows the company to add power and ground pins necessary for upcoming 125- and 133-MHz versions. Cypress hints that a large die and high power consumption forced IDT's move to a larger TQFP. Both of these future speed targets are "magic numbers": 125 MHz is one-eighth the bit rate of Gigabit Ethernet, and 133 MHz is twice the speed of the 66-MHz PCI buses that now appear in communications equipment.

These performance targets are at the edge of the toggle rates you can achieve with low-voltage TTL, and companies will in the not-too-distant future move to HSTL (high-speed transceiver logic) and SSTL (series-stub-terminated-transceiver logic). Even more radical architectures are now in the planning stages. These architectures include dual-port RAMs with one port offering a zero-latency bus for a µP interface and the other supporting double-data-rate (DDR) transfers for a DSP. Multiport-RAM packaging alternatives also include DIP, PLCC, PQFP, and BGA.

Cost reductions

Cypress has aggressively moved its higher density dual-port RAMs to an eight-transistor (8T) bit structure, whereas IDT continues to use the six-transistor, two-resistor (6T2R) approach. The 6T2R approach traditionally delivers smaller die for a memory array of a certain density, but those differences disappear as processes near 0.2 µm. The 8T structures have lower standby power consumption, which suits applications in which you want to increase system reliability by eliminating heat-dissipating fans (Reference 2). However, both dual-port structures are still larger than the six-transistor and four-transistor, two-resistor (4T2R) cells that commodity SRAMs use, which need not support multisourced read and write accesses (Figure 2).

Motorola has harnessed 4T2R cells as the foundation of its dual-port product line. The 1- and 4-Mbit separate-I/O NetRAMs offer distinct read and write data buses that share a common address bus. Motorola promotes its 1-Mbit dual-I/O NetRAMs as primary alternatives to true multiport RAMs; 4-Mbit versions will follow. NetRAMs lack asynchronous ports; both ports must run at the same speed, or, at a minimum, you must derive them from the same clock. Also, the parts are slower than Cypress' and IDT's fastest devices. But if none of these criteria are important to you, you should consider NetRAMs for their higher density and lower cost potential.

To the outside world, a NetRAM looks like a standard synchronous dual-port RAM. All of its addresses, data, and control signals are latched on the rising clock edge. Internally, however, the memories read or write one port's information on the rising clock edge and the other port's information on the falling clock edge. Motorola reports that it hopes, by early next year, to offer devices for sampling that eliminate the port-to-port clock dependency, but the internal data phase-shifting that enables the simpler cell structure may always keep NetRAMs at a speed grade or two lower than an 8T or 6T2R, dual-port equivalent.

IDT has its own lower cost product line, a bank-switchable dual-port memory (Figure 3). In addition to simplifying the cell structure, IDT eliminates the port-contention logic that a true multiport contains. (This logic handles cases in which both ports simultaneously attempt to read and write or write the same array location.) Instead, these 64kX16- and 32kX16-bit asynchronous devices in 5 and 3.3V versions subdivide into four banks. One of the port's controls manages each bank. Bank management takes the form of either software semaphores or hardware bank-select signals, and interrupts and mailboxes support interport communication.

For lower densities, you should also consider integrating multiport RAM onto your ASIC or PLD (see sidebar "Embed it"). Higher performance, lower power consumption, reduced board space, and eliminated packaging expenses are all potential benefits of this approach. Unlike DRAM, SRAMs are process-compatible with standard logic, so you don't have to grapple with a short list of foundry sources or trade off logic switching speed. Your actual cost savings and performance, however, depend on how the logic vendor implements its on-chip RAM.

If multiport RAMs are the on- and off-ramps of the network, the CAM is its traffic cop and navigator. Think of the CAM as a search engine—a sort of "silicon Yahoo." Instead of your giving the CAM an address and the CAM's returning data to you, you provide the CAM with the data that you are searching for, and it returns an address and other information related to the first match it finds.

The earliest CAMs were basic in their operation. These CAMs began with the early 1990s' LANCAM family from today's CAM-industry leader, Music Semiconductor. Data to match (the comparand), comparison instructions, and match results all traveled across a single bus with separate pins for control and match-flag functions. CAM array densities extended only to tens of kilobits, and only one global mask register existed to disregard specific bit values during match operations. These devices' close-to-100-nsec seek times were adequate for the data rates and network loads of the time.

CAMs found their first widespread usage in Layer 2 routers. Before 1993, only three classes of IP (Internet Protocol)-address allocation existed (Figure 4), so the number of mask registers could be small and still deliver fast searches with minimal mask-change overhead. As network administrators added active nodes, the router's software updated the CAM table with the IP addresses and corresponding ports. When a packet came through with an appropriate destination address, the CAM output the port value.

Times have changed. Routers now handle a number of Layer 3 and 4 functions, such as network-address-translation (NAT), firewall, URL, applet blocking, and other security protocols. They also handle protocol translation; quality of service; and additional data types, such as telephony and streaming audio and video. These added responsibilities mean that the CAM array contains more types of data, which increases both the array size and the number of required mask registers. They also mean that seek performance must accelerate, because routing algorithms access the CAM several times for each packet.

Binary-CAM vendors are now offering samples of chips with densities of 1 Mbit and beyond and fast seek times even with 66-MHz clock rates. Although performance, power, cost, and board-space advantages favor a single-chip device, minimal- or no-glue depth expansion supports multichip modules (Picture).

CAMs also incorporate varying degrees of automatic array updating. Previously, to add data to a CAM, you first had to find an unused location within the array (stored data can also consist of valid and aging bits) and then manually store the information in that location. Some newer CAM architectures automatically store data when you issue the Learn command; they also occasionally support an Unlearn command. This ability eliminates the time-consuming free-location search. A few CAMs even automatically output the data's location in one cycle as part of the Learn command.

If the CAM array is full, does the CAM automatically discard old data and replace it with the new information? This cache-controller-like capability might be valuable in some cases, but it is expensive to implement. Therefore, CAM manufacturers do not currently offer it. Because the Learn command is costly both in the required on-chip logic and the necessary test time for each device during manufacturing, lower cost variants often eliminate it. CAMs alert system logic to full and almost-full (with user-configurable threshold) status via status registers, output flags, or both.

If you think a dual-port RAM's 8T or 6T2R cell structure is more complex and expensive than that of a standard SRAM, wait until you see a nine- or 10-transistor binary-CAM bit (Figure 2c). The CAM uses these extra transistors to implement the XNOR compare. XNOR outputs combine in a wired-OR fashion to generate the match bit, and some CAMs also support a multimatch output. CAM bits are expensive real estate, so they find limited use for supplemental functions. More commonly, CAM outputs become index addresses for a lower cost commodity SRAM or DRAM that stores this additional data. Comparand, instruction, result, and control buses are often distinct on newer CAMs; in lower cost variants, their widths may be less than the internal data width. In those cases, multiple bus cycles read or write the entire data sequence.

The mask

Classless interdomain routing (CIDR) and NAT of nonroutable IP addresses for LANs have extended the life of 32-bit IP Version 4 (IPV4). By dissolving rigid class boundaries, CIDR more efficiently uses the available IPV4 address space. However, this approach increases the corresponding seek burden on CAMs and control logic, because every address bit is potentially significant, and a few global mask registers are insufficient for the task. CIDR instead uses the "longest-prefix-match" technique.

Enter ternary CAMs. In these devices, each data bit contains not only a cell storing the 1- or 0-bit value but also a corresponding mask bit indicating valid or invalid status. This approach instantly halves the maximum number of stored addresses for a given-sized CAM array and makes the seek circuitry more complex. But ternary CAMs have proved themselves equal to the task of overcoming these drawbacks: Thanks to 0.25-µm manufacturing processes, vendors have announced 1-Mbit devices with sustained 66-Mbps, 64-bit search performance. Even more complex CAMs and logic to control them are on the way (see sidebar "Memory, logic, or a little of both?").

Just as with multiport RAMs, lower cost CAM alternatives also exist. Motorola's 256-kbit and 1-Mbit CAMs are standard SRAMs with on-chip logic that runs a hashing algorithm beginning at the array midpoint and successively zeroing in on the matching data. The device assumes that you order data from lowest to highest value in successive array locations, so each update requires a time-consuming reorder step.

Seek time using hashing or derived algorithms is also nondeterministic because the time it takes to match data depends on the number of successive recursive-search steps the logic must execute until it determines whether a match exists. However, if your design needs moderate performance in which worst-case seek times approach 200 nsec and if table updates are infrequent, these devices may offer a cost-effective approach to implementing a wide, dense CAM function, such as in asynchronous-transfer-mode applications. Kawasaki LSI and UTMC Microelectronics also sell CAM longest-prefix-match hashing-logic engines that interface to discrete or embedded SRAM and DRAM arrays.

Even more radical cost-reduction options may soon appear. Embedded-DRAM pioneer Mosaid Technology hopes to begin sampling a DRAM-based ternary CAM by year's end. Instead of using a 17-transistor SRAM ternary-CAM cell, Mosaid will employ a 6T DRAM cell structure (Figure 2d). Mosaid claims that, after an initial pipeline latency akin to a standard DRAM random-access time, its DRAM-based CAM will sustain 66 million searches/sec.

Mosaid's system can initiate CAM refresh when it isn't otherwise accessing the CAM. Alternatively, the CAM can self-refresh and alert its status to the system via hardware flags. With respect to increasing bandwidth, Mosaid officials comment that DDR techniques, such as those that the company's DDR synchronous DRAMs pioneered, are an obvious approach. Mosaid also plans to support single-cycle learn-plus-match and glueless depth expansion.

Table 1—CAM and multiport-RAM suppliers and offerings

Author info

You can reach Technical Editor Brian Dipert at 1-916-454-5242, fax 1-916-454-5101, e-mail bdipert@pacbell.net.

REFERENCE

1. Dipert, Brian, "SRAMs strive to specialize," EDN, Nov 5, 1998, pg 62.

2. Dipert, Brian, "Embedded memory: the all-purpose core," EDN, March 13, 1998, pg 34.