RTL tools take design planning to a higher level

RTL tools let you make some chip-design decisions before logic synthesis. Knowing what kinds of EDA tools are available and what they can and can't do will save you time and money.

By Jim Lipman, Technical Editor -- EDN, 8/5/1999

Engineers like to make design decisions as early in the design process as possible. Good decisions early on help define design parameters and eliminate incorrect design paths. A decade ago, commercial logic-synthesis tools from companies such as Synopsys focused on digital-chip analysis and design planning at the gate level. Analysis at the gate level is sufficient for design complexities to around 50,000 to 100,000 gates. Unfortunately, system-on-a-chip (SOC) complexities reaching into the tens of millions of gates have made gate-level design planning inadequate.

Making design decisions at the RTL, before synthesis, is desirable. However, without the structural information that is part of a gate-level design description, it is hard to estimate design parameters, such as on-chip timing delays, power dissipation, and chip size. Despite this difficulty, you do have some EDA tools available to help you make presynthesis design decisions. (This article does not cover RTL tools for simulation, code enhancement, and code coverage. For a discussion of both code-enhancement and -coverage tools, see Reference 1. RTL simulators provide information about a chip's speed but are more useful for functional verification and do not give the type of design-planning information this article discusses.)

Designing at an RTL and a gate level are very different. RTL-design descriptions, such as the Verilog example in Figure 1a, include logic operation on a clock-cycle basis along with an implied design architecture. A logic-synthesis tool takes the RTL description and converts the design to a gate-level description (Figure 1b). Synthesis preserves the architecture and attempts to meet user-defined constraints, such as area and timing, in the gate-level description. The RTL design is technology-independent; it includes no process information or information about what design library you will use to implement the design. Logic synthesis creates a gate-level description using cell-library information. Logic synthesis uses a targeted library, with its implicit target-process information, to determine which library elements are available for the design and to synthesize a circuit that meets your design constraints. Although logic-synthesis tools have made possible an orders-of-magnitude improvement in design productivity—directly leading to SOC-design feasibility—inherent problems exist in today's typical logic-synthesis-based chip design, resulting from timing models used during different design stages.

Figure 2 shows a typical synthesis-based design flow. When you invoke a synthesis tool, it has no concept of the design's physical implementation. However, to meet timing constraints, synthesis tools use a statistical wire-load model for the targeted cell library (Reference 2). This model uses estimates for parasitic-interconnect and load-dependent delays that are average values based on previous designs using this technology. Although statistical wire-load models may have been adequate for most designs greater than 0.5 µm, with deep-submicron processes at 0.35 µm and smaller, these models are inaccurate. After you physically implement a design with place-and-route tools, the resulting logic may have very different timing characteristics, resulting in either a waste of silicon or a design that fails to meet timing requirements. The former problem wastes money; the latter definitely means redesign, resynthesis, and another place-and-route run. Synthesis and place-and-route iterations are expensive in time spent and in financial cost, both in real money and in "lost-opportunity time."

Floorplanning tools you use before or after synthesis can create better wire-load models for the synthesis tool. These "custom wire-load models" are based on placement data that the floorplanner creates. Because they are design-specific, custom wire-load models are more accurate than statistical models although still not as accurate as back-annotated parasitic data you obtain from an actual placed-and-routed chip. RTL perform-ance-estimation tools need to have some type of floorplanning capability to be able to predict electrical performance with any reasonable accuracy.

At the RTL, you have a description of a design's behavior. You get structural information only after logic synthesis. True topological data comes only after physical implementation. The design's constraints, which include speed, power dissipation, signal-integrity effects, and reliability, depend on process, cell-library population, and design placement and routing. RTL estimation of these parameters is a daunting task. If you can plan your design at the RTL, you accomplish many things. You can do "what-if" analyses to determine what design architecture best meets your chip's electrical specifications. In addition, RTL estimation helps you decide which cell library to use for your design. You can supply information to the logic-synthesis tool that can help achieve timing convergence and minimize synthesis and place-and-route iterations. Finally, you can get an estimate of chip size for a specific process technology that, along with speed and power estimates, helps you decide which chip package to use and gives an indication of chip cost. The goal of many chip-design companies is to have the right methodology and design tools in place to allow these companies to "sign off" a design at the RTL. RTL sign-off would indicate reasonable confidence that a designer would not have to make subsequent RTL changes to meet chip specifications (see sidebar "How real is RTL sign-off?").

RTL design planning

You do have a few EDA tools available that do some level of design planning at the RTL (Table 1). In general, the tools fall into two categories—those that use a "quick synthesis" step to estimate physical layout and those that do not. A few examples of these tools show how each can make RTL electrical-parameter and size estimations.

Tools that use a fast logic-synthesis stage include Synopsys' Chip Architect and Avant!'s Planet-RTL and recently introduced Jupiter. You can use Chip Architect at a number of places during your design—before generating RTL code ("black-box" planning), at the RTL, and at the gate level (Figure 3). Black-box planning uses hard cores, physically defined blocks, and designer estimates of RTL-block (soft-core) area and timing. The tool uses the hard- and soft-core information along with some coarse global routing to help you floorplan the final chip and to estimate chip performance. At the RTL, Chip Architect works on RTL code that you have not yet functionally verified. The tool performs a fast synthesis to generate a gate-level representation. According to Synopsys, this synthesis is five to 10 times as fast as the synthesis done by the company's Design Compiler logic-synthesis tool, with results that correlate within 20% of Design Compiler. After the quick-synthesis step, Chip Architect refines the floorplan you did during black-box planning and updates its estimates of chip size, timing, and power consumption. Gate-level planning with the tool uses blocks that have gone through a full logic synthesis with custom-wire-load models, which generates final-cell placement in each RTL block. Chip Architect takes the finished gate-level blocks along with the hard cores, synthesizes a clock tree, and outputs a final floorplan.

Similar to Chip Architect, Planet-RTL lets you do architectural exploration, RTL design partitioning, and perform-ance evaluation. Planet-RTL, like Chip Architect, also works with complete and incomplete logic blocks and has built-in quick synthesis to provide a preliminary chip floorplan. From the floorplan, the tool supplies custom wire-load models and synthesis scripts for subsequent full logic synthesis. Replacing Planet-RTL, Avant!'s newest RTL design-planning tool, Jupiter, combines features of Planet-RTL and Nova-ExploreRTL, Avant!'s tool for RTL-quality evaluation. (Avant! calls this evaluation "design authoring.") With Jupiter, you first check your code for language consistency, synthesis compatibility, and compliance with proper design practices. The tool then does a quick synthesis, again around 10 times faster than a normal synthesis, to get a preliminary floorplan, physical chip-pin assignment, global routing, and timing budgets for the various chip blocks (Figure 4). The quick-synthesis and preliminary-floorplan capabilities of both Chip Architect and Jupiter help you estimate your chip's physical, timing, and power characteristics without spending the time required for a full-chip logic-synthesis run.

In the nonsynthesis camp of RTL design planners is Tera Systems' TeraForm. The tool looks at an RTL block and infers structure for the block in the form of TeraGates, supersets of leaf cells that are building blocks for complex logic functions. Each TeraGate represents an optimized way of implementing a specific logic function. Using interconnected TeraGates in place of a quick-synthesis step, TeraForm does many of the same design tasks as Chip Architect and Jupiter—floorplanning, area and timing budgeting and estimation, custom wire-load models for synthesis, global routing, and pin-level optimization (Figure 5).

You also use IC Wizard, Aristo's "floorplan-synthesis" tool, for estimating chip electrical parameters at the RTL. The tool optimizes physical-chip floor-planning. Like Chip Architect, you use IC Wizard at various design stages—architectural, RTL, gate level, and physical—for block-level physical planning. At each stage, the tool generates multiple floorplan alternatives with user-defined timing, area, and power constraints. In each alternative, the tool optimizes physical parameters, such as block size, shape, location, and pin assignment. As you continue your design, the layout provides increasingly accurate information for area and performance estimation. At the RTL stage, IC Wizard helps determine an optimum block-level layout that meets your design constraints. The layout also provides block-boundary timing information to a logic-synthesis tool that gives better results than synthesis using only statistical wire-load models.

One type of RTL design-planning tool that has seen some measure of success is the power-estimation tool. Although some silicon vendors have proprietary RTL power-estimation tools, two companies, Sente and, more recently, TransEDA, have introduced commercial RTL power-estimation and optimization tools that include no logic-synthesis step.

Sente's Watt Watcher, first released in mid-1996, and Peak Watcher work at both the RTL and gate level. Watt Watcher estimates static and dynamic power for an entire chip and for individual chip modules. The tool does its estimates by inferring structure—in other words, making an assumption about what gate-level logic you would need to implement a specific logic function. Using the inferred structure and target-library information, Watt Watcher's power estimates, according to Sente, are within 20% of the power measured on silicon. Although you can use the tool in either a probabilistic mode or a simulation, most Sente customers use Watt Watcher in the more accurate simulation mode. Peak Watcher extends the power estimation and analysis to peak-power use on a cycle-by-cycle basis. Sente states that Peak Watcher's accuracy is within 30 to 35% that of silicon. The most recent Sente RTL tool, Watt Smith, lets you optimize your chip for minimum power. Using subprograms called "WattBots," Watt Smith identifies parts of the circuit in which you can reduce power consumption, computes how much power you can save in these sections, and recommends design changes you can make to obtain the power reduction.

Earlier this year, functional-verification-tool vendor TransEDA announced its own RTL power-estimation tool, PowerSure. Using actual circuit activity during RTL simulation as an input, the tool estimates power based on node capacitance, clock frequency, supply voltage, and circuit switching data. You can also use PowerSure on multiple simulations of the same circuit and sort the results of the simulations by power consumption. The current version of PowerSure depends on user-defined power models to get power estimation reasonably close to what you would see in actual silicon. Without these models, you can make best use of the tool by getting relative power dissipation between different implementations of a block. The next version of PowerSure, due out later this year, will include some form of block-structure inference to better model power consumption.

Author info

You can reach Technical Editor Jim Lipman at 1-925-606-1370, fax 1-925-606-1563, e-mail ednjim@earthlink.net.

REFERENCE

1.Lipman, Jim, "Covering your HDL chip-design bets," EDN, Oct 22, 1998, pg 65.

2. Kurup, Pran, Taher Abbasi, and Ricky Bedi, "It's the Methodology, Stupid!," Bytek Designs Inc, pg 26.