Scheme extends DDS phase-shift resolution

Mary McCarthy, Analog Devices Inc, Limerick, Ireland -- EDN, 8/5/1999

Direct-digital-synthesis (DDS) devices find wide use in instrumentation and communications applications. Rather than using a baseband converter to modulate data in a communications system, you can use a DDS device. Such a device has onboard phase registers that accommodate phase-shift keying (PSK). In communications applications, the phase shifting is in steps of 45° (µ/4 differential-quadrature PSK) or 90° (quadrature PSK). The device has enough resolution to generate these phase shifts. In instrumentation applications, the required phase shifts vary, depending on the system under development. Some applications require extremely accurate phase shifts. The phase registers in a DDS device are typically 12 bits wide, resulting in a phase resolution of 360°/4096, or 0.088°. However, by using the frequency register as in Figure 1 to perform the phase-shifting, you can increase the phase-shifting resolution to 32 bits.

If the DDS device has two frequency registers, you can use one to generate the output signal and the other to generate the phase shifts. By using the frequency register to perform phase-shifting, the phase-shifting resolution becomes 360°/2^N, where N is the resolution of the frequency register. Many DSS devices have 32-bit-wide frequency registers. You can therefore phase-shift the output signal with a resolution of (83.82X10^-9°). For example, if register FREQ0 contains the output-frequency value, then you can set FREQ1 to FREQ0+Q, thus phase-shifting the output signal by Q. Under normal conditions, FREQ0 supplies the phase accumulator of the DDS device. During phase-shifting, you select FREQ1 for one MCLK cycle, resulting in phase shifting the output signal by Q.

You can phase-shift the output signal by 0 to 360°. However, the frequency registers should not contain a value equal to or greater than 180°. Thus, to perform phase shifts greater than 180°, you must use the phase register along with the frequency register. You can set the phase register to 180° while using the frequency register to obtain the fine phase-shift resolution. The phase register and FREQ1 register serve as coarse and fine tuners, respectively. You use both registers in unison to perform the phase shift. For example, for Q phase shift in the output signal, PHASE+FREQ1=Q+FREQ0. You set PHASE to 180° and FREQ1 to Q+FREQ0-180°.

A DDS device has associated pipeline delays. When you select a frequency or phase register, a pipeline delay exists before you see a change at the DAC's output. In some devices, the latency from the phase register to the DAC's output is different from the latency from the frequency register to the DAC's output. With such devices, an intermediate phase shift occurs because the phase shift from either the FREQ1 or PHASE register occurs before the phase shift from the other register. In other DDS devices, such as the AD9830 and AD9831, the latency from the frequency and phase registers to the DAC's output is the same. Therefore, no intermediate phase shift occurs. The plot in Figure 2 shows the performance of the circuit in Figure 1, using the AD9830/9831 DDS device.

The master clock to the DDS device runs at 5 MHz. The device generates a 312.5-kHz output signal. The phase shift of the output signal is 270° at points b, d, and f in the plot. Because the PHASE register in the DDS device comes after the numerically controlled oscillator (NCO), you must keep this register selected until the next phase shift takes place. The FREQ1 register comes before the NCO, so you need to select it for only one MCLK signal. The AD9830/9831 has four phase registers, so you can use two of them to perform the phase-shifting. For the plot in Figure 2, PHASE0 and PHASE1 are the selected registers. At Point b, the output phase shift is 270° PHASE0's setting is 2048-180°, whereas FREQ1's setting is 1.5625 MHz (equivalent to 312.5 kHz+90°). Selection of FREQ1 and PHASE0 occurs at Point a, with FREQ1's selection lasting one MCLK cycle, and PHASE0's selection a continuous one.

At b, the phase and frequency values have propagated through the DDS device, causing an output phase shift of 180+90=270°. At c, FREQ1's selection lasts one MCLK cycle, and PHASE1 becomes selected, with a value of zero. PHASE1 causes an output phase shift of -180° (PHASE1-PHASE0= 0-180°). At d, the output signal's phase shift is-180+90=-90=+270°. At e, FREQ1 becomes selected for one MCLK cycle while PHASE0 is again selected. This selection produces an output (f) phase shift of 180+90=270°. (DI #2387).