Binary counter uses LSB feedforward

Robert Carter, Siemens PLC, Congleton, Cheshire, UK -- EDN, 8/5/1999

A typical synchronous binary counter contains a series of flip-flops, each of which changes state when all least significant bits (LSBs) are logic 1. This repeated AND function is the Achilles' heel of the binary counter. A designer has two choices: Use a ripple AND function (Figure 1), or a parallel AND function (Figure 2). The ripple AND function is slow, but the parallel AND function is hugely wasteful of gates and places a large fan-out burden on the LSBs of the counter. Note that, in typical CMOS gate-array technology, AND gates with more than four inputs are made up of combinations of gates. The configuration in Figure 3 combines the best features of both approaches.

The key to combining the two methods is to recognize that an AND function, not including the LSB of the counter, has two whole clock cycles to complete and then simply bring in the LSB in parallel with a further two-input AND gate. The approach in Figure 3 is generally beneficial when the counter is wider than 6 bits. This application is for a 32-bit error counter using 2-?m CMOS or a 140-Mbps plesiochronous-digital-hierarchy test set. You can extend the technique (to more than 15 bits or so) to propagate the LSBs in parallel; this extension would give the ripple path four clock cycles to settle. The downside of this method is that next-state errors would occur if you needed a resettable counter, though you can usually design out the requirement for such a counter at the system level. (DI #2388)