Restore dc to NRZ sigmals

Jay Kirschenbaum, Columbia University, New York, NY -- EDN, 10/28/1999

For NRZ signals, ac amplification is preferable to dc amplification, because ac amplification is usually more economical and has greater immunity to drift. However, ac processing has the disadvantage that ac coupling removes the dc reference level of the digital data stream. As Figure 1 shows, if a long stream of ones or zeros appears at the amplifier's input, the output droops after a period determined by the RC time constant at the input. This problem makes it necessary to include a dc-restoration circuit following the ac amplifier.

The circuit in Figure 2 restores the dc level that the amplifier removes and eliminates droop, even if long strings of ones or zeros appear in the data stream. The circuit also provides additional amplification, increasing the signal to ECL levels. Synchronous clocking gives the circuit good immunity to noise in the data channel. Tests reveal that the circuit operates satisfactorily at clock speeds from dc to 1 GHz.

IC₁ is an MC10E416 five-channel line receiver, which boosts digital signals from a minimum of 50 mV p-p to ECL levels. The input circuit of each channel of IC₁ is a differential amplifier, which responds when the signal level at the true input swings past the signal at the complementary input. In Figure 2, the input data stream goes to the D₀ channel. The complementary input ₀ connects to the V_BB pin, which is at –1.3V. The true input D₀ connects to bias voltage V_D through 50W. V_D is also nominally –1.3V, but you can tweak it to compensate for device characteristics. IC₂ is an MC10EL31 flip-flop. Both ICs are specified to 2 GHz. The logic level at D_IN transfers to Q_OUT at the positive transition of the signal at CLK_IN. Resistor R₃ and the 50W pull-down resistor, R₁, form a voltage divider that puts D₀ above or below ₀ by half the expected input-voltage swing. The value of R₃ is a function of the swing of the input signal. For example , assume D_IN has the value 100 mV p-p. If R₃ is 370W, and Q_OUT is at logic zero (–1.75V), the voltage divider sets D₀ 50 mV below ₀, and Q_OUT stays at logic zero as long as these conditions prevail.

Now suppose that logic one appears at D_IN. This condition simultaneously puts D₀ 50 mV above ₀, and Q_OUT switches to logic one (–0.9V) at the next clock transition. When this condition happens, the R₁-R₃ voltage divider holds D₀ 50 mV above ₀, and Q_OUT stays at logic one until the next transition to logic zero. Voltage droop disappears, and the dc reference of the digital signal re-establishes itself. Moreover, the circuit amplifies the 100-mV swing of the digital signal to ECL levels. Because the circuit triggers only when the clock edge appears, it's highly immune to noise in the data channel. At power-up, one transition from logic zero to logic one and one transition from logic one to logic zero are necessary at the amplfier input to put the circuit in a defined state. After that sequence, the circuit faithfully follows the input.

Proper timing between the data and the clock is important to reach the maximum operating speed of the circuit. Ideally, the clock edge should arrive at IC₁ as soon as the data-setup time is over, switching Q_OUT and pulling up D_IN as close to the data transition as possible. The theoretical upper limit on the operating (clock) frequency is a function of the propagation delay through the circuit (825 psec at 25°C). Data transitions must be spaced at least this far apart, so the maximum clock frequency is 1.2 GHz. Tests show that the circuit operates successfully at clock frequencies of dc to 1 GHz and data frequencies of dc to 500 MHz. The tests used a square wave for the clock input and a synchronous square wave of a lower frequency at the data input. The circuit restores the dc level and amplifies the signal to ECL levels over the entire test range. (DI #2434).