Manchester co-decoder fits into 32-macrocell PLD

Antonio Di Rocco, Siemens ICN Spa, L'Aquila, Italy -- EDN, 1/6/2000

Manchester encoding is common, and this scheme erases the dc-spectrum component present in an NRZ signal in baseband transmissions. An important application is in Ethernet-interface adapters, in which several kinds of media-attachment units interface with OSI layers. Many commercial transceivers work on all physical layers of the IEEE 802.3 standard. Figure 1 and the corresponding source code realize a customized version of the 10BaseT standard in which the physical layer is a coupled stripline in a backplane. Figure 1 shows the simple schematic of the LAN controller.

With an 80-MHz external clock, the 32-macrocell PLD implements a complete Manchester co-decoder at a 10-MHz bit-speed rate. You can download the VHDL source code.

The Manchester coder comprises an XOR gate between the transmitted data from the ?C data_in) and the internal 10-MHz clock. Both the data_in and coded output lan_out signals are synchronous with the 10- and 80-MHz clocks, respectively. Asserting a high at the "10" input enables the coder.

The decoder's operation is more complicated than that of the encoder. A behavioral simulation (Figure 2) shows the internal signals that are involved in the decoding process. Note that the spike on the "cd" signal is not a true spike; it appears only in the behavioral simulation and disappears in postlayout simulation. The signal "in_trans" is a short trigger pulse that occurs at every positive and negative "lan_in" transaction. These pulses trigger a filter maker that generates an impulse signal called filter, and each pulse of this filter signal lasts 75% of the bit interval. The end of each filter pulse marks the start of a pulse of a 10-MHz recovered clock. The design generates decoded data by sampling the data stream with the rising edge of the recovered clock. After a bit violation, or when "data_in" remains a one or a zero for more than 100 nsec, the system deasserts the carrier-detect signal, "cd." Many ?C families require that five or six recovered clock pulses are present after the system deasserts the carrier-detect signal. To conserve space in the PLD, this design roughly multiplexes the recovered clock and the 10-MHz system clock. (The 68360 ?P tolerates one pulse with no aspect of duty cycle.) The carrier-detect signal is the multiplexer controller. The 80-MHz clock has no stability requirements, and the system tolerates jitter on 10-MHz Manchester-coded signals. (DI #2462)