Verification tools give insight into HDL code performance

-- EDN, 1/6/2000

You can manage a range of design-verification tools for designs written in the Verilog or VHDL hardware-description languages with Transeda's Verification Navigator. You can use the integrated verification environment to apply code-coverage analysis, test-suite optimisation, circuit-activity analysis, and coverage analysis of finite-state machines. Transeda's first offering was a code-coverage product. The current version is simulator-independent and language-neutral (VHDL or Verilog), and it provides metrics that allow you to judge how well your code is executing in simulation and to measure the effectiveness of testbench code. A separate module lets you optimise the test suite, allowing you to execute the most effective tests first, giving you a greater chance of finding faults early and reducing test time. An incremental facility permits you to make changes to accommodate design changes while running only the tests you need for the alterations. For low-power-design concerns, the suite includes circuit-activity analysis that can give you insights, charting signal and block activity during simulation, into the effectiveness of the power-management steps you implemented at RTL design. You can correlate this activity check back to source code. The suite also includes facilities to handle finite-state-machine design, automatically recognising finite-state-machine structures and monitoring transitions to gauge the effectiveness of verification of these structures.

Transeda sees finite-state-machine design as sufficiently important to release a separate debugging tool, State Navigator, for the purpose. Language- and simulator-neutral, State Navigator can debug multiple communicating finite-state machines and annotate simulation results on state diagrams. You can obtain a representation of the machines' behavior in sequences, which Transeda says gives you verification at a higher level of abstraction. Static verification by code analysis before simulation checks for unreachable and "dead" states, and the product also features transition and expression coverage. Future versions of State Navigator will let it formally check finite-state-machine attributes.

State Navigator prices begin at $25,000, and Verification Navigator prices begin at $20,000.

Transeda, +44 1703 683500, www.transeda.com.

-by Graham Prophet