Verify SOC RTL blocks with workstation/accelerator

-- EDN, 1/6/2000

With RTL blocks in system-on-chip (SOC) ASIC designs becoming larger, the need increases for verification speed at RTL, according to hardware-accelerator manufacturer Ikos. Its Ares product, a "personal" hardware accelerator (Picture), has a capacity of 1.6 million simulation primitives, or about 3 million RTL gates. (A primitive is on the order of a two-input NAND gate.) The device compiles 50,000 gates per minute, yielding a seven- to 25-times speed increase over software RTL simulators. Ares partitions your design description in VHDL or Verilog into a portion that is synthesisable to the primitives that the Ikos system uses and a behavioural portion. The synthesisable portion compiles into the Ares accelerator, and the behavioural portion compiles into a conventional HDL software simulator running on the host workstation to which the Ares box is coupled. The process preserves RTL names and the hierarchy of the design, simplifying debugging. It can therefore support mixed-level, dual-language descriptions, and it also supports incremental compilation for fast iterations when tracing bugs. The base unit, with seven of Ikos' hardwired custom processors, will cost $139,000. You can double the capacity by adding a second card to a system.

Ikos, +44 1344 306565, www.ikos.com.

-by Graham Prophet