IC-place-and-route tool protects your (signal) integrity

-- EDN, 2/17/2000

Adding to the unique and innovative FixedTiming capabilities it introduced last year with its Blast FusionIC-layout tool, Magma Design Automation is adding features that ensure signal integrity (see "New tools add muscle to chip physical implementation," EDN, April 29, 1999, pg 18). These features will become available in March. With the current tool, FixedTiming allows BlastFusionto generate a pre-place-and-route timing-sign-off report that the software guarantees it will meet or beat from a Verilog netlist and appropriate constraints and library data. The objective: no place-and-route iterations.

The software accurately predicts timing before layout and operates using a memory-resident data model that allows it to concurrently perform optimization, layout, parasitic extraction, verification, and static-timing analysis. The tool operates on area and gate and routing track size to meet its estimate.

The new signal-integrity features provide automatic detection and correction of crosstalk, electromigration, and antenna-rule violations by adjusting track spacing and feature size on the fly. None of this comes cheap: Three-year time-based licenses start at $330,600 a year.

Enhancements promised for the second half of this year include gain-based RTL synthesis and the ability to detect and correct power-based integrity problems. The gain-based RTL synthesis applies the company's FixedTiming approach to the entire implementation flow—from synthesis to place-and-route—using a consistent data model and ensuring accurate timing early on. Gain-based RTL synthesis determines delay based on capacitive gain, rather than on absolute parasitics.

Magma Design Automation, www.magma-da.com.

—by Michael C Markowitz