EDA tool automates small-block test-vector generation

-- EDN, 2/17/2000

Mentor Graphics' FastScan MacroTest tool addresses a major concern of designers of complex system-on-chip ICs: enabling fast, high-volume testing of large numbers-often hundreds-of small embedded cores and memories. Most embedded-core test-development approaches incorrectly assume that the embedded cells' input and output ports are accessible to the tester. Providing access, ideally without adding significant numbers of pins to the IC, can substantially add to a chip's size and complexity and can introduce propagation delays that severely penalize performance. To mitigate these problems, designers have resorted to manual test-pattern generation, but that approach is error-prone and significantly increases product-development time.

FastScan MacroTest addresses these concerns by using on-chip scan hardware. The $50,000 test-development tool converts core-level simulation patterns from an HDL simulator into scan vectors without additional logic. You save the core's stimuli and responses as an ASCII file and submit the file to FastScan MacroTest. The tool analyzes each pattern and searches back from each core input to find a scan flip-flop or primary input. When the tool has justified and recorded all of the core's input and output values, it moves to the next simulation pattern, continuing until it has converted all such patterns. The process for finding observation points is similar. Design changes do not create significant additional test-development work; the tool generates new scan patterns from the existing simulation vectors.

Mentor Graphics, 1-503-685-7000, www.mentor.com/dft.

-by Dan Strassberg