Cascoded stack yields multiple voltages

Clayton Grantham, National Semiconductor, Tucson, AZ -- EDN, 3/16/2000

Although the cascode voltage-reference configuration in Figure 1 may seem obvious, the choice of R₁ and the bypass capacitors is critical. At first glance, stacking up references of the same voltage to produce a collection of voltages seems straightforward. However, nothing comes without precautions and an understanding of limitations.

As a case in point, the CMOS references used in this circuit have a 5.5V supply-voltage limitation. The circuit operates at 12V, which exceeds the limitation; thus each of the individual references must proportionally scale down the 12V input. IC₂'s 5V output powers IC₁, IC₃'s 7.5V output powers IC₂, and IC₄'s 10V output powers IC₃. Similarly, the references take their ground potentials from references beneath them in the cascode, to keep the total supply span for each IC below 5.5V.

The line-regulation errors of IC₁, IC₂, and IC₃ are near perfect, because their individual V_IN potentials come from a solid voltage source. The input source of 12V has a range of 10.2 to 14V, but if it dropped below 10.2V, each output voltage would be accurate until the input source dropped to within 200 mV above each stack voltage. For example, if the input source were at 5.2V, the 2.5 and 5V outputs would be within specification and the 7.5 and 10V outputs would be close to 5.2V. In this way, as a 12V battery collapses, external circuitry dependent on the lower voltages would still be functional.

Let's examine R₁ and its limits. The LM4130 sources current very well (to 20 mA), but it sinks only 10 µA. Thus, R₁ is a resistive pull-down for IC₂'s quiescent current (50 µA). R₁ must be a maximum of 25 kW to keep IC₂ biased for worst-case specs over temperature. This 100-µA bias current also keeps IC₃ and IC₄ biased. The ICs of the stack roughly share a single quiescent current, as opposed to a parallel configuration that would draw four times the quiescent current. It is also true that each output source current has a ripple effect from previous ICs in the stack. Thus, cumulatively, the voltage outputs (2.5, 5, 7.5, and 10V) can source as much as 20 mA (5 mA from each output). Load currents of the lower references have effects on the voltages of the ICs stacked above. If the output impedance (0.075W) of the LM4130 were not very small, then its effect would create a large crosstalk error, with one output causing another to vary. For example, with the 2.5V output loaded with 20 mA and accounting for the Z_OUT effects of both IC₂ and IC₃, the worst-case change in the 10V output is 3 mV, or 0.03%.

The bypass capacitors C₁ through C₄ have a secondary function, other than input bypassing, that overcomes another limitation of the cascode configuration. They compensate the internal LM4130 output. This output stage is a common-source PMOS FET with local feedback that reduces the output impedance beyond 100 kHz. Ceramic, tantalum, or aluminum-electrolytic capacitors work to keep the stack of voltage references from start-up instabilities and oscillations. Another limitation of the cascode arises if the lower voltages (2.5, 5, and 7.5V) become grounded. Any continuous short circuit would produce excessive power dissipation in the LM4130. The optional 47W series resistance in the 12V line protects the ICs under worst-case conditions. Note that despite the limitations, the accuracy of the stack voltages tracks the LM4130's accuracy. And, as with accuracy, the temperature-coefficient errors do not degrade up the stack. (DI #2501).