PLD architectures run error-correction intellectual property

-- EDN, 4/13/2000

Aiming at the infrastructure side of the wireless communications business, Altera has added a range of error-correction cores to its intellectual-property-for-PLD offering. The series offers the benefits of programmable logic for this class of applications in areas such as wireless base stations, in which reconfigurability, lower development costs, and design convenience score. The series includes Reed-Solomon, Viterbi, and Turbo components. The Reed-Solomon compiler supports six types of Reed-Solomon cores at encoding speeds greater than 1 Gbps and decoding speeds of 800 Mbps. You can parameterise it and generate test vectors for your chosen configuration through Altera's MegaWizard plug-in. Once you set the parameters, compilation yields an optimised netlist. Next in the complexity level is the Viterbi decoder, a core that is available for a decoder to operate as fast as 100 Mbps with an integrated additive white-Gaussian-noise test generator. Most complex in the hierarchy of forward-error correction is the Turbo encoder/decoder core, which supports data rates higher than 2 Mbps and targets third-generation wireless systems. You can fit the product into an EP20K200E device in the Apex 20K family and evaluate the functions through a download using the OpenCore system from the company's Web site at www.altera.com/Ipmegastore.

Altera, +44 1494 602000, www.altera.com.

-by Graham Prophet