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EDN's first annual programmable-logic directory
EDN's first annual PAL, PLD, and FPGA directory highlights the architectures available for your next design. Here's help in sorting through the multitude of devices and the overabundance of marketing hype.
By Brian Dipert, Technical Editor -- EDN, 8/17/2000
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Logic devices in many ways epitomize the fundamental technological "driver" of consolidating more and more functions into fewer and fewer components at the lowest possible cost. Logic devices are unlike microprocessors and memories, which are both dominated by a few high-volume standardized products with little to no possible hardware customization. In contrast, logic devices stand out because of the almost infinite variation of unique implementations they provide. This flexibility allows you to differentiate yourself in today's competitive market by targeting specific price, performance, power-consumption, form- factor, and other specifications.
The logic-device family further subdivides into several categories: discrete logic, simple and complex PLDs, FPGAs, and standard and custom-cell ASICs. FPGAs, SPLDs/PALs, and CPLDs are all programmable-logic devices, although their internal architecture implementations differ. This article uses the term "programmable-logic device" to refer to the entire range of products and specifies a category via its acronym.
Programmable-logic devices are the fastest growing segment of the logic-device family for two fundamental reasons. Their ever-increasing logic gate count per device "gathers up" functions that might otherwise spread over a number of discrete-logic and memory chips, improving end-system size, power consumption, performance, reliability, and cost. Equally important is the fact that in a matter of seconds or minutes you can configure and, in many cases, reconfigure these devices at your workstation or in the system-assembly line. This capability provides powerful flexibility to react to last-minute design changes, to prototype ideas before implementation, and to meet time-to-market deadlines driven by both customer need and competitive pressures.
Programmable-logic devices do not have the long lead-times, up-front NRE charges, minimum-order quantities, or inventory complexity of ASICs. As per-gate cost decreases and as the number of gates per component increases, programmable-logic devices are beginning to make significant inroads into traditional ASIC territory. System designers and manufacturers are only beginning to explore and exploit in-system reprogrammability, either to correct errors and upgrade functions once the end system is in users' hands or to use a fixed number of logic gates to implement multiple functions. This latter technique is known as reconfigurable computing.
The programmable-logic industry is relatively young and highly varied. Just as companies use programmable logic's flexibility to differentiate themselves, a number of semiconductor vendors have developed unique PLDs and FPGAs to address an intersection of performance, power, integration, and cost targets. This diversity is perhaps the most complex challenge facing you, because, in many cases, you must deeply understand each programmable-logic architecture before selecting one that meets your needs. The market leaders are increasingly driving de facto industry standardization, thus simplifying the selection task.
Highly complex programmable-logic architectures rely extensively on design-automation software to produce optimum results for end-system parameters. Prioritizing these parameters depends on the application. Often, for example, designs targeting low power, high performance, or minimal gate count significantly differ from each other. Ideal design-automation software:
- isolates you from the internal device-architecture details;
- enables you to prioritize your design goals and optimizes the software's operation based on this priority ordering;
- efficiently uses silicon resources;
- requires little to no manual intervention;
- quickly compiles and recompiles a design; and
- minimizes or eliminates timing and pinout changes between compilations.
The technical superiority of a programmable-logic vendor's silicon products and the comprehensiveness of the vendor's documentation are not the only determinants of the vendor's success or failure. Equally important are the depth and breadth of the company's internally developed and third-party software-tool support.
Burgeoning amounts of on-chip RAM and single-die ASIC/programmable-logic hybrid devices, along with predictable Moore's Law integration trends, are contributing to the explosion of programmable-logic devices' effective gate counts. These factors are finally making a reality of the long-held vision of systems on chips. To exploit silicon capability in a time frame that still meets time-to-market requirements, many designers are turning from traditional low-level state-machine and schematic-entry synthesis to high-level languages, such as VHDL and Verilog. These approaches provide the additional benefit of enabling design reuse. Yet, just as with high-level versus assembly-language software development, high-level logic design decreases development time but produces lower performance and less efficient gate usage. Again, robust software support for silicon architectures is a must.
Another technique that has become more popular over the last few years involves leveraging the already-completed designs, or IP, of another company instead of designing your own circuits. The convergence of accelerating silicon gate count, increasing system functions and standardization, and decreasing time to market is driving this approach. Perhaps the biggest IP hurdles still to overcome are legal rather than technical, although robust test and verification suites and core interoperability between vendors and among silicon architectures are important.
| FPGAs | PALs & PLDs |
| Actel | Altera |
| Altera | Atmel |
| Atmel | Cypress Semiconductor |
| Lucent Technologies | Integrated Circuit Technology |
| QuickLogic | Lattice Semiconductor |
| Xilinx | Xilinx |
ABEL=Advanced Boolean Equation Language
BG=BGA=ball-grid array
CABGA=ceramic BGA
CAM=content-addressable memory
CG=PBGA=plastic BGA
CLCC=LCC=ceramic leadless chip carrier
CPGA=PG=ceramic PGA
CPLD=complex PLD
CQFP=ceramic QFP
CS=CSP=chip-sized package
DIP=dual inline package
DLL=digital delay-locked loop
EBGA=enhanced BGA
EEPROM=electrically erasable PROM
EPROM=erasable PROM
FBGA=FG=FPBGA=fine-pitch BGA
FCBGA=flip-chip BGA
FIFO=first in, first out
FPGA=field-programmable gate array
GTL=Gunning transceiver logic
HQ=high-heat-dissipation QFP
HSTL=high-speed transceiver logic
IP=intellectual property
ISP=in-system programmable
JTAG=Joint Test Action Group
LUT=look-up table
LVDS=low-voltage differential signaling
MIPS=millions of instructions per second
NA=not applicable
NRE=nonrecurring engineering
PAL=programmable-array logic
PBGAM=plastic BGA, multilayer
PC=PLCC=plastic leaded chip carrier
PCI=peripheral-component interconnect
PDIP=plastic DIP
PGA=pin-grid array
PLA=programmable-logic array
PLD=programmable-logic device (product-term based)
PLL=phase-locked loop
PROM=programmable ROM
PQ=PQFP=plastic QFP
QDR=quad data rate
QFP=quad flatpack
RISC=reduced instruction-set computer
ROM=read-only memory
RQFP=power QFP
SOIC=small-outline integrated circuit
SONET=synchronous optical network
SPLD=simple PLD
SQFP=shrink QFP
SQFP2=power-shrink QFP
SRAM=static random-access memory
SSOP=shrink small-outline package
SSTL=stub-series terminated logic
TPD =propagation-delay time
TQ=TQFP=thin QFP
TSSOP=thin-shrink small-outline package
UART=universal asynchronous receiver-transmitter
VHDL=very-high-speed integrated-circuit hardware-description language
VQFP=VTQFP=very-thin QFP
| For more information... | ||
| For information on subjects discussed in this article, use EDN's information-request service . When you contact any of the following manufacturers directly, please let them know you read about their products in EDN. | ||
| Actel 1-408-739-1010 www.actel.com Enter No. 316 | Altera 1-408-544-7000 www.altera.com Enter No. 317 | Atmel 1-408-441-0311 www.atmel.com Enter No. 318 |
| Cypress Semiconductor 1-408-943-2600 www.cypress.com Enter No. 319 | Integrated Circuit Technology 1-408-434-0678 www.ictpld.com Enter No. 320 | Lattice Semiconductor 1-503-268-8000 www.latticesemi.com Enter No. 321 |
| Lucent Technologies 1-908-582-8500 www.lucent.com Enter No. 322 | QuickLogic 1-408-990-4000 www.quicklogic.com Enter No. 323 | Xilinx 1-408-559-7778 www.xilinx.com Enter No. 324 |
| Other companies mentioned in this article: ARC Cores, www.arccores.com | ||
Author info
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Contact Technical Editor Brian Dipert at 1-916-454-5242, fax 1-530-937-8147, bdipert@pacbell.net.
REFERENCE
1. Dipert, Brian, "Low-cost programmable logic: How low should you go?" EDN, March 16, 2000, pg 123.
2. Dipert, Brian, "The best (or worst?) of both worlds," EDN, Nov 11, 1999, pg 139.
3. Dipert, Brian, "Figuring out reconfigurable logic," EDN, Aug 5, 1999, pg 103.
4. Dipert, Brian, "Synthesis shoot-out at the EDN corral," EDN, Sept 11, 1998, pg 95.
5. Dipert, Brian, "Counting on gate counts? Don't count on it," EDN, Aug 3, 1998, pg 52.
6. Dipert, Brian, "Moving beyond programmable logic: if, when, how?" EDN, Nov 20, 1997, pg 77.
7. Dipert, Brian, "Programmable logic: Beat the heat on power consumption," EDN, Aug 1, 1997, pg 57.
8. Levy, Markus, "Processors drive (or dive) into programmable-logic devices," EDN, July 20, 2000, pg 107.
