Gated clock has duty-cycle control

Paul Kemp, University of Colorado, Colorado Springs, CO -- EDN, 8/17/2000

The circuit in Figure 1 produces clock pulses with variable duty cycle from a gated clock. The output of the circuit, pulse, is always 180° out of phase with the clock input. When the delay-logic elements, IC₅ and IC₇, have the same propagation delays, the duty cycle of the circuit's output is 50%. The circuit produces gated clock pulses when the gate input, gate, is high and the active-low reset, reset_n, is high. Increasing the propagation delays of the increase-duty-cycle delay-logic element, IC₅, causes an increase in the duty cycle of the gated-clock output, pulse. The decrease-duty-cycle delay-logic element, IC₇, reduces the duty cycle of the gated-clock output. Listing 1 is a Verilog model of the circuit; a Verilog testbench verifies the circuit's function. A pair of delay-logic elements is modeled with 20 delay lines of 1 nsec each. The testbench instantiated this operation. A simulation (Figure 2) used Cadence Verilog-XL. A 20-MHz clock serves as the input clock. The select signals in Figure 2 for the increase-duty-cycle delay-logic element, IC₅, and the decrease-duty-cycle delay-logic element, IC₇, correspond to the number of 1-nsec delay elements inserted into the delay paths. Thus, a select value of 12 corresponds to a 12-nsec delay. (DI #2554)