News and New Products

IP model strives to reduce time to market, increase yield

By Bill Schweber -- EDN, 2/17/2005

More complex ICs, tighter design geometries, and deadline pressures mean that each design spin is getting tougher. To meet these challenges, Virage Logic has combined IP (intellectual-property) and silicon in the Silicon Aware IP model, which may tip the scales toward meeting these challenges. Virage based the model on its Star memory system, which offers self-test and repair.

The new model combines physical IP, including memories, logic, and I/O, with embedded infrastructure IP to provide test, diagnostic, repair, and yield improvements at processes of 130 nm and below. According to Virage Chief Executive Officer and President Adam Kablanian, “As chips get more dense and complex, yields can drop below 10%. With this approach, designers can go to advanced processes and designs and hit high-yield targets.”

The company has agreements through leading foundries and ODMs (original-device manufacturers) to implement the system. For example, Virage integrates its IP with process-aware extensions from PDF Solutions Inc (www.pdf.com) so that designers can tailor the Silicon Aware IP to address the inevitable problems of processes and fabrication technologies. Thus, it can prioritize and target, with understood trade-offs, the detrimental effects of yield-reducing factors, such as multiple contacts, polysilicon shorts, opens in critical areas, and metal Layer 1 shorts in critical areas, in a designated fab. Using this approach, Kablanian says, “You can do advanced design on an immature process and get acceptable yields.”

Virage Logic Corp, www.viragelogic.com.