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Synopsys Woos Verisity Users with Migration Service
Online staff -- Electronic News, 2/14/2005
For users of Verisity's Specman Elite testbench product wishing to migrate to Synopsys' popular VCS RTL verification tool, Synopsys has begun a Native Testbench (NTB) migration service, the company reported today.
NTB converts Specman Elite verification environments to VCS environments in order to achieve up to 5X faster verification performance. When combined with Synopsys’ DesignWare verification IP and support for the Synopsys reference verification m (RVM), VCS is meant to allow a complete RTL verification solution by creating constrained-random stimulus along with assertions to monitor the design and perform functional coverage analysis.
NTB deploys a single-compiler architecture to simultaneously optimize design, testbench, assertions and coverage, aimed at allowing higher verification performance compared to fragmented environments, and also enables full interoperability between the OpenVera language and the SystemVerilog standard.
“Creating a sophisticated verification environment requires the most capable bug-finding technologies, the fastest verification performance and a proven methodology based on broadly supported standards,” said Janick Bergeron, a scientist in the verification group at Synopsys, in a statement.
The migration service is available now and includes conversion of e verification environments to VCS NTB environments; tools, language and methodology training; custom verification IP development; and eVC migration to the Synopsys DesignWare Verification IP portfolio with support for a large number of protocols, including AMBA 3 AXI, AMBA 2 AHB/APB, Serial ATA and the PCI, USB and Ethernet families.
“Customers are increasingly moving away from proprietary point tools toward an integrated solution,” noted Farhad Hayat, VP of marketing for the verification group at Synopsys.
“The NTB migration service makes it easier for current Specman Elite users to take advantage of powerful bug-finding technologies in the Synopsys VCS solution and realize higher verification throughput and cost reduction,” he added.
Synopsys also announced today it is teaming with Mentor Graphics on a series of free “eScape to SystemVerilog” technical seminars to provide guidance to users of Verisity’s e language to transition to a standards-based verification methodology built on SystemVerilog.
