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Apache dynamic-power tool finds—and fixes—problems

By Michael Santarini, Senior Editor -- EDN, 2/22/2005

San Jose—The latest version of Apache Design Solutions, Inc.'s RedHawk dynamic power-analysis tool not only analyzes designs to find power problems and their impact on timing, but also locates and fixes power problems at the source, according to the company's president and CEO, Andrew Yang.

Most analysis tools have the ability to point out problems and tell you where they are occurring, but Yang said that with the new RedHawk-EV (extended version), Apache is taking the next step: Showing designers the source of power problems and then giving them the choice of fixing them.

Since its release in 2003, the RedHawk tool has garnered a bit of acclaim for its ability to perform full-chip power analysis. The company's previous top-line version of the tool, RedHawk-SDL added inductance analysis, could analyze with power-based constraints, and performed transient analysis.

Now with the EV version, Apache has extended the vectorless power-analysis capabilities of the tool so that it also does vectorless analysis on power-ground networks and accounts for timing issues such as slack on critical paths, in addition to timing-window and slew information. "We're taking this additional information to better understand areas in a design that are weak in timing and factor that into our vectorless analysis," Yang said.

Because the tool now analyzes all the major sources of power problems and their relation to timing, Apache has been able to add features that locate the source of power drops, Vdd or ground bounce, and was able to add to the tool features to fix problems at the source, Yang said.

The tool will find power-drop sources in a design and then allow users to do full-chip and regional nonuniform grid resizing. "In one area, the power-ground mesh network may be too loose, and we can tighten it," Yang said. "Conversely, it may be overdesigned or too tight, and we can loosen it."

Yang noted that the tool performs the resizing selectively on the power-supply network, avoiding the need to make adjustments to every layer.

To deal with leakage, most engineers just drown their designs with decoupling capacitors, Yang pointed out. The EV tool, however, doesn't reduce the number of decaps that are placed, rather it takes away unnecessary ones, but only if it will have no impact on timing.

Finally, the company claims it has upped the speed and capacity of the tool by adding caching technology and the ability to natively handle 45° geometries found in flip-chip designs and in Cadence's forthcoming X-Architecture routing.

The tool, which has verified designs in excess of 25 million instances, maintains accuracy within 5 to 10% of transistor-level simulation, Yang said.

The upgrade is free to customers of RedHawk-SDL; RedHawk-SD customers have to fork over extra cash.