FROM EDN EUROPE: And so proceed, ad infinitum

To begin with, Moore's Law was an interesting speculation. Then, when the semiconductor industry had demonstrated a decade or two of compliance with it, it became part of the landscape. Now, we tend to take it for granted. From time to time, we wonder how long the continuous reduction in feature size it describes can go on: clearly, there must be physical limits to the shrinking process at some point. But the industry confounds such thoughts and continues to deliver generation after generation of ever-smaller devices etched to their slivers of silicon. To the point that, as you read about this 0.13-micron or that 90-nm process, you may well think, "Do I need to know? If I am not having a system-on-silicon ASIC fabricated in the latest technology, need I care about what the process-of-choice is, right now? If I work with standard parts, what does it matter how they are built?"

From day to day, it may not matter very much what's inside the package. Indeed, vendors of some structured ASICs assure us that when we buy certain ASSP products from big-name standard-part vendors, what we are actually getting is one of their mask-programmed chips. You don't have to know how it's built as long as it does the job.

On a longer time scale, following the relentless progress of Moore's Law does help us to track the consequences of the ever-shrinking process trend. It enables us, year on year, to use ever-more sophisticated packaged functions. Through a kind of trickle-down effect, it also means that if we are using parts at the lower end of the complexity scale, we get ever-faster and more capable microcontrollers, memories, and so on, for pennies. If the shrinking had not continued beyond 0.35 or 0.25 micron, we might still be working predominantly with 5V logic rails. Some might argue that would be no bad thing. No silver lining is without its cloud, and chips built in 130-nm technologies are fragile little things - if their makers didn't surround them with ESD and voltage level protection, they would die very quickly when exposed to the real world. This is, in fact, such a concern that EDN's Analog Editor Joshua Israelsohn is currently looking at what options you have if you want and need "industrial strength" circuitry - an article that will appear in a forthcoming issue.

The whole process is subject to the phenomenon of our constantly-changing perspective. When we used chips built with 4- and 5-micron technology, we asked: "Can parts under 1 micron be made?" (They could.) Now, when most of what we use is built at 0.18 micron, moving to 0.13, we could ask, "Will things still work at 90 nm? Can the industry get 65 nm to work, or 45?" At this stage, though, there is an added layer of interest in watching the process: the extent to which the semiconductor vendors are betting their futures on some very arcane decisions. It's well-known that wafer fabs cost spectacular sums of money; but so too does development of the semiconductor processes themselves. And, it's a pipelined procedure. Right now, an advanced semiconductor vendor (any of them) is in volume production of 0.13 microns, is fairly familiar with 90 nm and beginning production with it; is well along with the development of 65 nm; and is looking hard at 45 nm. The economics of today's industry are such that several of these stages are being undertaken with partners and collaborators. Even so, the pace and the technical difficulty mean that decisions on materials and technologies are being taken long before hard data on their true behaviour is available. You know you have an increasing problem with, say, device leakage; you think you have route to a solution; but if it doesn't work, you will be years down the line, with hundreds of millions spent, before you find out. Even for the biggest of today's companies, the scale of the bet is such that there may be no way back.

There are signs that some industry figures are losing confidence in the process. Early last year, an IBM spokesman was quoted as saying that [the process of constantly shrinking silicon geometry] "had stopped breathing and turned blue, but no one has noticed."

Philips, on the other hand, recently revealed part of its strategy, which it has applied to low-power device development. Principal Scientist at Philips, Phillip Christie outlined the Virtual Design Flow, work that has enabled devices to be evaluated for use at 45 nm - well before detail tools such as compact models of transistors are available. At 45 nm, processes can only be designed by an integrated consideration of devices, inter-connect, logic and layout. The virtual design flow is - in effect - a simulation not of the silicon, but of the "process of designing a process". Many data points, based on sample device designs, are fed into the model, and the methodology is able to explore the design space for the process development. Using a timing-based analysis, very early exploration of coupled device and interconnect behaviour is possible, and technology development can move forward. Christie appears confident that using this approach, his company can arrive at the stage of selecting from all the multi-faceted options to establish a viable path to a process at 45 nm.

The end, it would seem, is not in sight. Not just yet, anyway.

 Contact me at gprophet@reedbusiness.com.