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FROM EDN EUROPE: Structured ASICs widen market reach
By Graham Prophet -- EDN Europe, 3/3/2005
With the disparate range of products on offer, it is not entirely clear that the "structured ASIC" market sector is indeed a single sector. LSI Logic and Altera mark two very different members of that grouping, and both have added new and more complex devices to their product ranges.
Altera has introduced the latest version of its HardCopy (called HardCopy II, which is confusingly the third generation of the product). It marks a departure from its predecessors in that earlier devices essentially followed the architecture of Altera's FPGA devices, but with the programmability stripped off. Relieved of the overhead of programming circuitry, a mask-programmed part could be built with equivalent logic in considerably less silicon area, at correspondingly lower cost. HardCopy II leaves behind the FPGA architecture - it looks a lot like an "old-fashioned" gate array - to achieve a further step up in density. However, Altera's promise of a turn-key conversion from an FPGA-based design is retained. A series of parts ranges up to 2.2 million "ASIC" gates, 8.8 Mbits of RAM, and over 350 MHz performance. There is no longer a 1:1 equivalence with the FPGA range. Depending on the mix of DSP with other logic, a given FPGA might map to more than one HardCopy part. The reverse is also true; in addition to viewing the parts as a cost-reduction path for a design executed in a programmable device, designs can target the HardCopy part from the outset. In this scenario, the FPGA becomes a prototyping vehicle and in this case, a selection of FPGAs might serve to prototype a given HardCopy chip. At the level of complexity that will be achievable in 2 million gates, physical synthesis will be required to achieve an efficient placement in the design. Altera notes that the design process will allow combinations such as specifying the HardCopy device as the target (maximising efficiency and performance) while also generating an FPGA configuration file for prototyping. This will not yield an FPGA layout of optimum efficiency, but Altera says it will be functionally equivalent. Features include memory interfaces for 233 MHz SDRAM, 1 Gbit/sec differential I/O and a range of high-speed serial interfaces. Used in volumes of 100,000, prices will be from $15 per chip, with an NRE charge starting at $225,000 for a conversion from an FPGA-based design.
LSI's RapidChip Integrator 2 series is also a family progression from earlier parts. Rapidchip is LSI's structured ASIC product, and the company says that it is finding applications in consolidating multiple chips (possibly FPGAs) into a single integrated design. It is also being used for designs that "could have been ASICs" in earlier generation technology but which are economically marginal in today's advanced high-density processes. The new family comprises eight base "slices" - pre-diffused wafers that are customised to a specific design by metallisation, in four layers. They feature separate areas of memory and logic; "matrix-RAM" memory is organised in blocks that can be combined in width and depth to any required configuration. Further memory can also be configured out of the logic array to provide small, local blocks. Designers can implement very wide or deep memory and still achieve 300 MHz speeds, LSI says. The highest density slice offers 7.9 Mbits of memory in 344 blocks of varying size; the corresponding peak level of logic density is 5.6 million gates. 250 MHz is quoted as the achieved system clock figure at 25 levels of logic. The devices' I/O features the usual range of high-speed serial interfaces, although LSI has not implemented SERDES on this series - that comes on a later release. There is also support for high-bandwidth interfaces to external memory, such as DDR2, QDR2, RLDRAM2, and FCRAM2, with controlled impedance and slew rates.
Three of the eight devices are in wire-bond packages, allowing the range to start from a per-chip price of around $40 (at 30,000 per year and upwards). The five most complex devices are flip-chip packaged, and the most expensive will be priced around $200 per device. Implementing a design would typically take from three to six months, LSI says.
Altera, +44 1494 602000, www.altera.com.
LSI Logic, +44 1344 413200, www.lsil.com.
