News and New Products

Structured ASIC offers memory-for-logic swapping

By Michael Santarini -- EDN, 4/28/2005

Configurable-core and structured-ASIC vendor eASIC Corp and its partner Flextronics Semiconductor have released structured ASIC that allows users to configure the amount of logic, memory and reprogrammable logic they need for a given design. The company’s executive vice president for marketing, Ronnie Vasishta, says that the company’s new FlexASIC fabric gives users the best of the FPGA and ASIC worlds: the density and speed associated with ASICs without the NRE (nonrecurring-engineering) costs and the programmability ease of FPGAs without the power and performance shortcomings. “FlexASIC offers a 25- to 30-times density improvement over FPGAs with power density and performance akin to cell-based design,” says Vasishta, claiming FlexASIC operates at approximately 400 MHz.

The FlexASIC architecture boasts a field of proprietary SRAM three-input LUT (look-up-table)-based logic cells, called eCells (embedded cells) surrounded by embedded-SRAM blocks, PLLs, an 8051 microcontroller, and ROM blocks. Configurable I/O surrounds all these blocks. The FlexASIC architecture allows users to swap eCells for extra SRAM if a design requires. For example, the biggest device in the FlexASIC family, the FA3000, boasts 3 million ASIC gates in the form of 92,000 eCells, or 194,000 LUTs, plus 2.8 million bits of embedded single-port SRAM (Picture).

Designers can configure some eCells after fabrication to reprogrammable-logic blocks. The companies program a device’s eCells, RAM, and embedded RAM during fabrication using “e-beam” technology, which customizes the vias between the sixth and seventh layers of the eight-layer process. The routing customization differs from programming the logic and programmable-logic blocks. The companies use a bit stream for this programming and can reload the blocks for debugging after fabrication.

The companies also built a clock tree into the fabric, which means that users need not build it but also that they can’t adjust it. The companies offer users two design flows to configure and program the devices. Using the first flow, designers feed a Verilog or VHDL netlist into Synopsys’ (www.synopsys.com) Design Compiler, which creates a gate-level netlist. Users then perform-chip resource allocation, assigning memory, clocks, and I/O on the design. Then, using a proprietary eTools suite, users perform mapping, placement and, with OEMed technology from Golden Gate Technology (www.ggtcorp.com), global routing. Users then perform final routing and finishing and BIST (built-in self-test) with eASIC tools. They can use any vendor tool to perform ATPG (automatic-test-pattern-generation) testing. With the second flow, users feed a Verilog or VHDL netlist into an eASICFlextronics-only version of Magma’s (www.magma-da.com) Blast SA, which incorporates the Aplus physical-synthesis tool. The tool performs synthesis and placement and then feeds into eASIC’s router, finishing tools and BIST. As with the other flow, users can perform ATPG with any vendor tool.

The companies currently fabricate the FlexASIC devices on STMicroelectronics’ (www.st.com) 130-nm process. The company claims there are no NRE charges for customers, and they will accommodate low-volume orders because they can implement a number of customers’ designs, even if targeting a different part number of the eASIC family, on a single wafer. Vasishta says that companies have ironed out the lithography and DFM (design-for-manufacturing) issues. The company offers a debugging technology, but customers can receive sample silicon as early as two weeks after tape-out so they can test their designs in real time in their systems. Package support for the family ranges from 100-pin TQFP to 896-pin FBGA; eASIC is currently receiving tape-outs from beta customers and expects prototyping silicon by May and production silicon by July.

eAsic, www.easic.com.

Flextronics, www.flextronics.com.