EDN 2005 DSP Directory: Targeted DSPs take aim

Welcome to the 2005 EDN DSP directory. This directory continues to grow at a substantial rate each year—so much so, that this year's edition comprises an annual update of companies and products that is available in both EDN's print and online editions and a comprehensive table listing devices and cores that is available exclusively on the Web. The table presents DSP-market offerings in a dense format, highlighting the latest developments in the market and providing an up-to-date listing of current and valid processor offerings. Feel free to share your thoughts for making the directory even more useful as the market continues to change.

According to market-research company Forward Concepts (www.fwdconcepts.com), the DSP chip market grew 27.2% during 2004. The wireless market accounts for almost three-quarters of that growth at 71.5% (up from 68% in 2003). It's noteworthy that most of the gains occurred in the first half of last year, because the (mostly) Chinese cell-phone makers had to deal with a glut of inventory. Forward Concepts has lowered its forecast for the 2005 DSP-market growth from 20 to 10%.

As signal-processing designs become more complex, device and IP (intellectual-property) vendors are developing and packaging bundled resources, platforms, or reference designs to demonstrate to designers how to use their products for specific applications. DSP vendors are committing serious design resources to developing reference designs, which continue to gain importance as tools to secure strategic design-in wins. These reference designs often go beyond samples and application notes—in some cases, to the point of turnkey implementations. Currently, finding a vendor's available reference designs is neither straightforward nor consistent within a company's product material. EDN plans to highlight reference-design information in this directory, and this year in its 2005 Microprocessor Directory, as well as in annual updates.

EDN has loosened the criteria for inclusion in the DSP directory to better accommodate the many ways to implement signal processing, including hybrid combinations of software-programmable DSPs, fixed-function devices, reconfigurable devices, and host microprocessors. Standard processor devices with multiple DSP and RISC cores and the development tools that support these devices continue to become more common. The current online table categorizes DSP offerings not by application space but rather by vendor. If you have ideas about column headings that would be more useful to your search for the perfect DSP product, please drop us a line. Likewise, if you have ideas for how to incorporate other types of signal-processing options, such as fixed-function blocks, reference designs, and platforms, please e-mail your ideas to us at dspdirectory@edn.com.

Over the previous year, Altera continued to extend its programmable-logic products and tools. The Hardcopy II line of structured ASICs features an FPGA front-end design methodology; Altera built the architecture around a fine-grained collection of transistors called HCells that support the seamless migration from an FPGA to realize the density, cost, performance, and power benefits of ASIC technology. Altera also unveiled the Stratix II EP2S180 device—its largest and fastest FPGA. Version 4.2 of the Quartus II design software includes new PowerPlay power-analysis and -optimization technology. Altera's SOPC (system-on-programmable-chip) software-development tools and IP cores help designers target applications in the communications, computer peripheral, and industrial markets.

Altera maintains Web resources, including FAQs, device and IP support, design-software support, and mySupport, with which users can create, view, or update service requests and manage software subscriptions or IP licenses. The Cyclone II DSP-development kit to assists developers with wireless-infrastructure, medical-diagnostics, imaging, and test-and-measurement equipment. In addition to a development board, the development kit includes the latest version of The MathWorks' Simulink software, Altera's DSP Builder, and the Quartus II design software. Altera provides reference designs for broadcast, automotive, computing, and wireless applications that designers can use to reduce design time and improve their understanding of Altera products' capabilities.

Over the previous year, AMI Semiconductor acquired DSPfactory, which focuses on the medical market, specifically in providing digital-signal processing as ASICs and standard products for ultralow-power medical wireless applications. It also introduced the Orela 4500 series, which targets DSP-based, mixed-signal audio systems to provide audio processing and exceptional sound quality for digital hearing aids that require sophisticated processing capabilities and advanced features. The BelaSigna 200 series targets high-performance DSP-based audio systems, such as wireless, industrial, and specialty headsets, and other ultralow-power, small-form-factor audio applications. AMI Semiconductor introduced bundled signal-processing algorithms for use with the BelaSigna 200, including streaming audio for wireless reception of high-fidelity stereo sound on Bluetooth stereo applications and telecom algorithms for communication in Bluetooth telecommunication headsets. The reconfigurable, DSP-based Toccata Plus system targets midrange to high-range hearing-aid applications.

AMI Semiconductor offers a suite of simulation, evaluation, development, and application tools for each of its devices. Evaluation and development kits include a board for rapid prototyping, evaluation, and testing; sample code demonstrating real-time algorithms; bundled UltraEdit advanced and integrated development editor with AMIS extensions; firmware support for developing real-time algorithms; a complete compilation-tool chain; low- and source-level debuggers; an EEPROM-manager-layout tool; and documentation. The Hybrid demonstrator board enables digital-hearing-aid developers to connect AMIS Orela 4500 series hybrids directly to transducers, switches, trimmers, and other peripherals to evaluate the real-world performance of their designs. The Advanced Headset reference design, which RF Micro Devices and AMI Semiconductor jointly developed, provides an end-to-end option for wireless streaming audio. The hardware incorporates the AMIS BelaSigna 200 DSP-based audio system with an integrated codec. Possible applications include streaming audio from a PC, notebook, portable audio player, or other analog source to a headset.

AMI Semiconductor's Orela 4500 series of DSP-based, mixed-signal audio systems is designed for use in hearing-aid applications that demand a high level of integration, excellent sound quality, low power consumption, and miniaturization. It supports selectable clock speeds, configurable sampling frequencies, and "smart" power management with a range of customizable features to enable hearing-aid manufacturers to optimize performance and power consumption. Orela 4500 systems consist of a 16-bit, fully programmable, dual-Harvard 16-bit DSP core; a high-resolution block-floating-point WOLA (weighted-overlap-add) filter-bank coprocessor that provides efficient processing to minimize power consumption; and an I/O processor with peripherals and interfaces that optimize the architecture for audio processing. Orela 4500 systems have multiple analog/digital inputs and outputs that enable interfacing to a variety of transducers, switches, potentiometers, and other devices.

The 16/32-bit Analog Devices' Blackfin embedded processor target the computational demands and power constraints of embedded audio, video, and communications applications. Based on the MSA (Micro Signal Architecture) that Analog jointly developed with Intel, the Blackfin Processor family combines a 32-bit RISC-like instruction set with 16-bit dual MACs (multiply/accumulate) units. Dynamic power management enables lower power consumption by allowing the simultaneous adjustment of system operating frequency and voltage under application control. Analog Devices' Crosscore tools support development for the Blackfin processors and consist of the VisualDSP++ development and debugging environment, EZ-kit Lite evaluation kits, EZ-Extender daughterboards, and emulators. Release 4.0 of VisualDSP++ incorporates TCP/IP and USB support, a processor configuration/start-up code wizard, and multiple-project management.

The recently available ADSP-BF534/36/37 devices are a functional extension of the ADSP-BF531/32/33 processors. The higher performance ADSP-BF537 offers more embedded memory, enabling higher throughput needs for embedded-system applications, such as video security/surveillance and industrial-environment-based distributed-control and factory-automation applications. The ADSP-BF536 targets low-cost connected devices, such as remote monitoring devices, VOIP (voice over Internet Protocol), and biometrics applications. The ADSP-BF534 processors' system peripherals include an integrated CAN (controller-area network) 2.0B controller; a two-wire interface controller; UART and SPI ports; external DMA request lines; 32-bit timers (some with PWM capability); a real-time clock; a watchdog timer; and a parallel peripheral interface. The ADSP-BF536/537 further extends these features by adding an integrated IEEE-compliant 802.3 10/100 Ethernet MAC and an enhanced DMA system for high network-bandwidth capability.

The five-stage-pipeline ARC 600 family of configurable and extendable cores provides embedded control, computation, and digital-signal-processing tasks targeting battery-operated and cost-sensitive consumer, networking, and automotive applications. The architecture includes memory options, such as single-cycle, closely coupled memories for instructions and data, as well as configurable instruction and data caches. Multiple 32-bit ports, including main memory, auxiliary registers, and closely coupled memories support external memory access. The architecture supports BVCI- and AHB (AMBA hardware bus)-configuration options.

The seven-stage-pipeline ARC 700 family of configurable cores combines a powerful 32-bit CPU and a full-featured DSP engine in a unified architecture to target the more demanding tasks of graphics, media codecs, and packet processing. The ARC 700 architecture supports embedded operating systems, such as Linux. It also supports memory options and extends external memory access via multiple 32- or 64-bit ports. ARC 600/700 DSP extensions include 16- and 32-bit MAC and saturating arithmetic instructions with access to configurable banks of XY memory. The ARC DSPlib library of custom instructions accelerates common DSP calculations.

The ARChitect processor configurator enables designers to create customized ARC-processor-core designs for specific applications. ARChitect enables designers to take advantage of ARC's configurable and extendible architecture without increasing project complexity or risk by supporting industry-standard SOC (system-on-chip) design flows and integrating with downstream tools, such as simulators, compiler/debugger testbenches, and prototyping platforms. The core's configurability allows designers to select only the features required for their applications, resulting in smaller devices that can consume less power than a fixed processor core. The core's extendibility allows designers to define custom instructions and extensions to accelerate critical code for higher performance, lower device frequency and power consumption, or both. The ARCompact 16/32-bit ISA (instruction-set architecture) can provide a 40% improvement in code density compared with a 32-bit-only ISA; designers can mix 16- and 32-bit instructions without an overhead impact. Many software-development-tool vendors, including ARC Metaware, Green Hills Multi, and Gnu support software development of the ARC cores. Operating-system support for these cores includes ThreadX, MQX, uCLinux, uItron, and Java.

ARM bases its VLIW (very-long-instruction-word) OptimoDE Framework, which it launched last year, on key technology it acquired from Adelante Technologies. ARM OptimoDE Data Engines are licensable IP with an associated tool environment, a datapath functional-resource library, and preconfigured microarchitectures with varying parallelism and performance. Designers can use OptimoDE, which targets high-performance embedded signal-processing applications, as stand-alone processors or in designs with microprocessor cores. It supports parallelism, a virtually unlimited datapath configuration (including mixed widths), user extensibility, and access to fixed-function or reprogrammable data engines. OptimoDE Data Engines are compatible with ARM's DSP Interface Specification, which describes the interfaces between the cores for mailbox-based command-and-control messaging and bulk data passing, debug and trace interfaces and protocols for multicore debugging, and software APIs for interprocessor communications.

By supporting reprogrammability, the OptimoDE design process enables designers to freeze the Data Engine architecture and continue to tune the algorithm through software changes. This approach enables multiple algorithms with similar requirements to use the same Data Engine hardware. Developers can reprogram OptimoDE Data Engines once they have committed the design to manufacture or they are shipping it in volume. They can regenerate code to accommodate incremental design changes or alternative algorithms without altering the underlying hardware architecture.

The tool environment enables designers to configure and extend the type and number of datapath-resource units. Designers may also configure the size and topology of local storage and the level of interconnect. ARM provides a C compiler and profiling-analysis tools that enable designers to program OptimoDE Data Engines in C or C++. The OptimoDE tool environment automatically generates simulation models that designers can use to verify the integration process, once the data engine is incorporated within a design. OptimoDE Data Engines are AMBA-compliant and work with a variety of ARM System IP.

Atmel's high-performance, 40-bit, floating-point, VLIW Magic DSP can perform as many as 10 arithmetic operations per cycle and enable a single-cycle FFT Butterfly. It provides native support for complex arithmetic and vectorial SIMD (single-instruction-multiple-data) operations. The dual-processor Diopsis 740 device integrates a Magic DSP and an ARM7TDMI microcontroller core with 1.9 Mbits of RAM. The product targets complex-domain, floating-point, high-precision, embedded-system applications, including professional-quality audio, speech processing for hands-free phones, radar-based automobile-collision avoidance, acoustic diagnosis of mechanical equipment, and software-based ultrasound scanners.

Over the previous year, Atmel has added features to the MADE (multicore-application-development environment) debugging capabilities. MADE, the Diopsis integrated development environment, includes C compilers for both ARM and Magic DSPs, a high-level Magic DSP macro-assembler/optimizer, an eCos RTOS, a library of C-callable DSP functions, and a unified debugging environment interfacing with a cycle-accurate simulator or a Diopsis board. The C-callable DSP library has grown from 75 to 125 functions. The library includes a variety of FFTs, IIRs, and FIRs on single-sample sequences or input-data streams; vectorial square roots; vectorial magnitudes; and vectorial arithmetic and trigonometric operations, and a reach set of matrix functions. Atmel also introduced two boards for the Diopsis DSP—the Test and Evaluation Board and a Dual Diopsis PCI mezzanine card.

Cambridge Consultants' configurable VLIW APE2 DSP targets adaptive datapath signal-processing applications. The company based it on a software-DSP-generator tool kit. APE2 targets consumer-market applications such as wireless, audio, and measurement systems by minimizing silicon cost and maximizing performance. For example, an APE2 configured for a hearing-aid application requires fewer than 20,000 gates and consumed less than 50 mW. Designers use the generator tool kit to configure a VLIW DSP from ready-to-use processing elements it draws from the APE module library together with dynamic datapath routing. The starting point for algorithm design is generally Matlab, and the same operations are simulated using the APE software-tool kit. Once the system is working, the tool kit produces an APE2 DSP in the form of a Verilog netlist, together with the assembly language to run the signal-processing task.

During the previous year, Cambridge Consultants extended the range of APE2 processing modules for math-intensive operations with trigonometric, vector, ratio, reciprocal, coordinate-transform, square-root, exponent, and logarithmic functions. These modules complement the MAC, ALU, radix-4 FFT, sequencing, I/O registers, and memory-interface modules that were already available. Designers can license the software-tool kit and transfer the APE2 technology into their teams. Alternatively, Cambridge Consultants can analyze a design's requirement and produce a silicon-ready APE2 IP core for integration into a licensee's ASIC project. APE2 license fees have no per-chip royalty.

Last year, Ceva announced the Ceva-X architecture framework, a scalable VLIW-SIMD DSP architecture targeting baseband and multimedia applications, such as 3G multimedia phones, PDAs, digital cameras and camcorders, DTV and high-definition DVD. The first implementation of the Ceva-X family, the Ceva-X1620, combines microcontroller and signal-processing functions in a variable-width (16/32-bit) instruction set. The Ceva-X1620 can simultaneously issue as many as eight instructions and offers high code compactness using SIMD concepts. The Ceva-XS1100 and Ceva-XS1200 are new complete systems built around this DSP architecture that include peripherals, interconnections, and interfaces to external memories, I/Os, and CPU systems. The Ceva-XS1100 and Ceva-XS1200 are two DSP subsystems built around the Ceva-X1620 DSP. These subsystems include a 3-D DMA coprocessor to better target multimedia applications. The Ceva-XS includes interfaces to Level 2 memories, APB peripherals, and a CPU system based on 64-bit AHB-Lite master/slave ports.

Ceva announced the Mobile-Media, a DSP-based multimedia platform that consists of a DSP core (based on Ceva-Teak or Ceva-X), a DSP subsystem (Xpert-Teak or Ceva-XS), and a set of optimized software modules that target the mobile multimedia market. The 16-bit-fixed-point, general-purpose Ceva-Teak DSP core features a dual-MAC architecture for complex signal processing. It includes built-in accelerators for FFT and Viterbi to target portable-multimedia and wireless-communication applications. Ceva built the Xpert Teak subsystem around the Ceva-Teak dual-MAC DSP core; it includes a power-management unit, an interrupt controller, general-purpose I/Os, timers, on-chip emulation, TDM ports, and a code-replacement unit. It also includes a 3-D DMA engine to support multimedia applications through video-related data transfers.

Ceva's fully programmable Mobile-Media platform supports H.264 encoding and decoding at full D1 resolution, 30 frames/sec, without any hard-wired acceleration. Other than the H.264 codec, Mobile-Media includes MPEG4, H.263, JPEG, and AAC codecs. Other audio codecs, such as MP3, WMA, AAC+, and AMR, are optional. Ceva also announced the Ceva-TeakLite-II, a revved-up DSP architecture based on its predecessor, the Ceva-TeakLite, to target 2G/2.5G handsets and optical-disk applications. Other improvements to the architecture include increased memory space and a higher level of system integration.

Each DSP is available as licensable-IP soft cores or silicon with development platforms that operate with PC/Windows, Unix/Solaris, and Linux operating systems. Ceva offers boards targeting specific applications, such as multimedia, audio, and communications, as well as algorithms and application libraries, such as speech codecs, audio, and video codecs. Last year, Ceva announced CevaNet, a partner program that includes more than 35 application, software, and EDA-tool vendors that provide Ceva DSP support. CevaNet focuses on software and algorithm developers, application developers, and software and system design/debugging-tool developers.

Fabless semiconductor company ChipWrights offers video-processing technology to reproduce lifelike imagery in mobile personal-entertainment products, digital video/digital still "dual cams," and high-demand video applications, such as security cameras and digital television. The new ChipWrights CW5521 SIMD processor combines a RISC processor, a parallel processor with 16 32-bit datapaths, enhanced video-sensor features, USB, audio-codec compact flash, and secure digital-card interfaces.

The ChipWrights development environment includes a software-development kit that integrates a compiler, a simulator, a profiler, a linker, and a debugger into the Metrowerks CodeWarrior integrated-development environment. The Reference Application Specific Libraries include resources for image processing, video and audio codecs, a ChipWrights BIOS, and development boards.

Cirrus Logic's 32-bit CS4961XX family features an audio systems processor that integrates a DSP with dual MACs; dual memory moves; dual index registered update; and log/exp assist. Optimizations for butterfly FFT, FIR, and IIR with CobraNet technology deliver uncompressed digital audio over Ethernet networks. Cirrus Logic supports a library of audio algorithms, including THX Ultra2, DTS ES 96/24, Dolby Surround Pro Logic IIx, and a modular programming environment for easy customization. Cirrus Logic introduced the Intelligent Room Calibration software for automatic speaker setup and room equalization using its CS495XX and CS494XX DSPs. The framework includes state-of-the-art decoders, virtualizers, surround simulators, and audio-enhancement algorithms. Cirrus Logic's DSP A/V-receiver reference design includes a library for firmware feature differentiation.

Cradle's 32-bit CT3000 family of programmable DSPs targets media-processing applications with a focus on video-surveillance applications, such as PC-based and embedded DVRs, IP streamers, and digital-video cameras. Other target applications include imaging and broadcasting. Over the previous year, Cradle introduced the CT3600 multiprocessor DSP family, comprising the CT3608, CT3612, and CT3616. Each device consists of two computational quads made up of processing cores, local data and instruction memory, and separate address and data buses. In the CT3616, the family's highest performing member, each quad consists of eight single-issue pipelined DSP cores and four simple RISC-like general-purpose processors. A three-tiered memory hierarchy increases performance predictability and scalability. Each quad includes 128 kbytes of shared data memory and 32 kbytes of instruction cache, which the four general-purpose processors share. Each DSP has its own local instruction memory- and data-register file that enables the cores to run fairly autonomously. The family provides an I/O subsystem consisting of 18 programmable 8-bit pin-groups that can support interfaces including video (CCIR601/656), audio (PCM), 10/100 Ethernet, and IDE. This family provides a DDR-SDRAM interface.

The CT3600 family uses the same multiprocessor DSP architecture as the CT3400, but it supports program execution at 1.5 times the operating frequency and can include twice as many computational elements. Power consumption is 1 to 5W depending on device size, application, and operating frequency. The DSP instruction set supports special video and imaging instructions. The SAD (sum-of-absolute-difference) instruction accelerates the processing of motion estimation, and the PIMAC (packed-integer-multiply-accumulate) instruction can perform 16 8-bit MACs in a single cycle.

Cradle's software-development-support infrastructure includes Version 5.0 of Cradle's integrated Rapid Development System, the Inspector graphical multiprocessing debugger, a full GCC-compliant compiler, a DSP intermediate compiler, a multilevel application profiler, and a cycle-accurate simulator. An optimized version of the open source eCos operating system is available. The Rapid Development System software-development kit supports Windows 2000, XP, and NT.

This year, DSP Architectures began offering the full military version of the MILDSP24 and MILtMMU24 general-purpose signal processors. These products support extended-temperature and 75-MHz operation, which is higher than the commercially available 65-MHz DSP24. DSP Architectures has implemented a program to offer commercial (DSP24), military (MILDSP24), and rad-hard (RHDSP24) silicon cores for customer-proprietary designs.

The high-performance DSP24 vector-processor chip and its associated IP cores for signal and image processing in the frequency domain target applications that perform operations on large arrays of data. It is a pass-based processor, with each function valid for one complete pass. Each operation code defines a basic flow for the desired operation that repeats for multiple pairs of data to complete one pass. For typical array-processing applications, such as FFTs, the device sets up a function code (for example, BFLY32). Radix32 butterfly and then clocks the whole data array into the DSP24 and applies the function to it. Latency occurs when you implement the DSP24 functions, which the MMU24 automatically compensates for when you use it in a system. The pipelined systolic structure allows you to cascade multiple DSP24s for increased performance and higher radices. This structure permits high-speed operation on an unlimited array size with support for enhanced read-only FFT, double-length FFT, dual FFT, and stacked FFT to reduce latency.

Equator's MAP series of video-centric processors, which includes the MAP-CA, BSP-15 and the BSP-16 processors, performs the central functions of digital imaging, communications, and media applications as software. The BSP-16 device is the newest member of Equator's BSP (Broadband Signal Processor) family, which includes the DataStreamer DMA engine, an onboard IDE controller, and Ethernet MAC, all operating as fast as 500 MHz. The VLIW BSP-16 CPU performs computationally intensive numeric and multidimensional matrix operations in video- and signal-processing operations. It can run video- and image-processing algorithms, operating systems, network stacks, middleware, virtual machines for Java, and Internet browsers.

The iMMediaTools software-development-tool kit consists of a suite of software tools, device libraries, and utilities for creating and optimizing video-centric applications. It features a VLIW tool chain with an ANSI C/C++ compiler; drivers to implement advanced video features, such as PIP (picture in picture); native support for Linux; Windows CE drivers; support for optimized audio and video performance from C/ C++; a multiformat media-player infrastructure that supports trick play, PIP window, and graphics overlay; GDB source-level debugging; and an operating-system abstraction layer for codecs, application code, and player/recorder infrastructure.

Over the previous year, Equator introduced cost-reduced reference designs, including the Starfish and Babelfish set-top-box reference designs. The company expanded the platform's support for audio- and video-software codecs to include Windows Media Advance Profile, H.264, RealVideo, and aacPlus. The platform also includes support for additional conditional-access and DRM (digital-rights-management) capabilities, such as Windows Media DRM 10. Equator hardware reference platforms also include reference designs targeting IPTV (Internet Protocol television), digital home and consumer electronics, security/surveillance, and videoconferencing.

This year, Freescale introduced the MSC71xx family of DSPs, basing it on StarCore technology, with a DDR-SDRAM controller. This family of devices targets enterprise VOIP, IP PBX (private-branch-exchange), and network-edge and -access applications scaling from four to hundreds of channels in fractional or multiple T1/E1 increments. The family varies by peripheral sets, with the MSC7116 and MSC7113 targeting developers of Ethernet-only equipment. The MSC711x family of devices is pin-to-pin compatible and offers the same instruction-set and binary software compatibility with Freescale's StarCore technology-based MSC81xx family. It also provides Ethernet, DMA, and TDM communications peripherals.

The MSC81xx family of devices includes both high-performance single-core and multicore digital-signal processors. The single-core devices MSC8101 and MSC8103 and the multicore devices MSC8102, MSC8122, and MSC8126 are all software-compatible. Both product lines target computationally intensive infrastructure DSP applications, including packet telephony, media gateways, multichannel modem banks, and third-generation wireless systems. The newest devices, the MSC8122 and MSC8126, are available with 300-, 400-, and 500-MHz core speeds, and Freescale bases them on 90-nm-process technology. The MSC8122 and MSC8126 can deliver 8000 DSP MMACS at 500 MHz, yielding an effective performance equal to 2 GHz.

Freescale also announced the addition of a 275-MHz speed to the DSP56321, a member of the DSP563xx family that can perform 550 MMACS when its Enhanced Filter Coprocessor is in use. This device maintains the same full temperature qualification of –40 to +105°C as its predecessors. Freescale's 24-bit, floating-point-architecture DSP563xx processor family targets wireless and wireline infrastructure and communications equipment, as well as packet telephony, professional audio, scientific test and measurement, industrial control, and healthcare related medical equipment. This family includes the DSP56321, DSP56311, DSP56L307, DSP56309, DSP56303, and DSP56301.

Freescale also introduced the 56F8100 series of devices for price-sensitive industrial and consumer applications. It bases the series on the 56800E hybrid digital-signal-controller core, which integrates the instruction set of a DSP with the control functions of an embedded microcontroller in a single core. The 56800 family targets applications that traditionally use 16-bit microcontrollers but also require DSP functions, such as point-of-sale and voice-recognition applications, digital-telephone-answering devices, motor-control systems, and applications requiring voice, audio, or data processing. The 56800E core enhances the 56800 architecture by providing five times the performance (up to 200 MIPS) at one-third the power consumption of the original core, and by doubling code density. It offers expanded memory addressing for as much as 4 Mbytes of program memory and 32 Mbytes of data memory.

Freescale's CodeWarrior tool suite from Metrowerks, including the SmartDSP operating system and CodeTest software-analysis tools, provides development support for all of these processor families. Freescale's Smart Packet Telephony Hardware Reference Design is for small- to large-scale media-gateway equipment capable of voice, fax, or modem data services. System architects may use this evaluation platform to assess the capabilities of Freescale's DSPs for voice compression and echo cancellation. Trinity Convergence provides the VeriCall software framework to provide a flexible, open architecture for VOIP designs based on Freescale's MSC711x and MSC81xx family of DSPs, the PowerQuicc family of integrated communications processors, PowerPC host processors, and C-3/C-5 network processors.

Hyperstone's HyNet32S, a scaled-down version of the HyNet32XS networking processor, features the same E1-32XSR RISC/DSP core but adds PCI bus functions. Hyperstone builds the HyNet series of networking processors around the E1-32XSR core and adds integrated peripherals supporting high-speed communications (Ethernet, Real Time Ethernet, Serial, ATM), additional internal RAM, video interfacing, PCI support, DMA, and more. These processors target applications requiring high-speed signal processing; communications, including real-time Ethernet; or both.

Hyperstone's E1-16XSR/32XSR RISC/DSP processors provide seamless integrated RISC/DSP functions for any application requiring a high-speed microprocessor coupled to a high-performance DSP. These processors feature dual execution units (RISC/DSP) in a pipelined architecture sharing the same registers. Developers can transparently mix RISC- and DSP-specific programming. Devices execute RISC/DSP instructions with a high degree of parallelism, resulting in high throughput. Typical target applications for use are telephony, video, digital cameras, general signal processing, and more.

Hyperstone offers hardware- and software-development tools, including a real-time kernel, a C compiler, an assembler, a linker, an EPROM formatter, a source-level debugger, and several hardware target boards. Also available is the HyNetOS full-featured operating system, which includes a collection of communication-protocol stacks, including real-time Ethernet; a file system; and memory management. Hyperstone is also offering an application-specific hardware target board for use in the development of real-time Ethernet applications, such as Ethernet Power Link.

The ZSP Products Division of LSI Logic is a licensor of signal-processing cores and products. LSI Logic also offers standard product offerings for lower volume designs and prototype implementations. The ZSP processor architecture targets 3G wireless handsets, multimedia, and networked voice appliances. ZSP Solution Partners augment the technology with software tools, EDA-modeling support, and a portfolio of application software. Over the previous year, the ZSP Products Division expanded its signal-processor family to include the ZSP540 licensable core, the less-than-$4 (high volumes) LSI403LC standard product, and the off-the-shelf, bundled silicon/software Z.Voice-729 package for VOIP applications.

The high-performance, power-efficient, quad-MAC, six-ALU ZSP540 DSP core delivers 1.2 GMACS on a 0.13-micron process. The ZSP540 core includes the Z.Turbo technology for application-specific acceleration targeting 2.5/3G baseband processing, multimedia wireless/mobile devices, WLAN, and VOIP applications. The LSI403LC DSP targets cost-sensitive applications requiring low power consumption and can gluelessly interface to popular microprocessors. Its large on-chip memory eliminates the need for external memory. ZSPneo, a new entry point to the ZSP road map, targets cost-sensitive applications that require control processing beyond 8- and 16-bit-microcontroller performance but cannot tolerate the cost and overheads associated with a 32-bit microcontroller. ZSPneo also targets one- or two-channel VOIP, audio players, speakerphones, wireless application processors, toys, and servo and vehicle controls.

LSI Logic's DSE (DSP Solutions Engineering) team, a worldwide network of DSP systems experts, provides direct consultation, training, application notes, bulletin boards, and access to the KnowledgeBase FAQ database. DSE works with ZSP Solution Partners to develop reference designs and sample systems in the form of boards, RTL, and SystemC models.

Microchip this year released to production 15 devices in the dsPIC30F DSC (digital-signal-controller) family. The two sensor devices target space-constrained applications with package options as small as 6×6 QFN. The nine general-purpose devices support a range of flash-program-memory sizes from 24 to 144 kbytes. The four motor-control/power-conversion devices feature a PWM and an ADC. Microchip also introduced a series of application libraries, including noise suppression, echo cancellation, speech recognition, and encryption that designers can evaluate for a $5 license fee.

Microchip's dsPIC30F DSC, a 16-bit modified Harvard machine, combines the control advantages of a microcontroller with the computation speed of a fully implemented DSP in a single-chip, single-instruction-stream architecture. All dsPIC30F DSCs execute from flash program memory and feature a familiar microcontroller architecture and design environment. The dsPIC DSCs feature flash memory, EEPROM, software stacks, a strong interrupt structure, mixed-signal capability, low-pin-count options, and real-time emulation. The dsPIC DSC also features dual-operand fetches, a barrel shifter, zero-overhead loops, and single-cycle 16×16 MAC with twin 40-bit accumulators.

The dsPIC30F tools operate seamlessly within Microchip's Mplab integrated development environment, a free tool suite that includes the Mplab ASM30 assembler and the Mplab SIM software simulator for writing and testing dsPIC30F code. Also available is the dsPIC30F Visual Device Initializer. A full-featured 60-day demo of the Mplab C30 C compiler is available in a download. Hardware tools include the ICE4000 Emulators, ICD2 in-circuit debuggers, and programmers to assist with in-circuit serial programming. Third parties have extended their lines of embedded cross-compilers to cover the dsPIC30F devices.

Morpho Technologies' MS1-16, an optimized rDSP IP core, targets high-performance wireless-infrastructure and power-optimized mobile devices, such as multimode wireless base stations and multimode 3G wireless handsets. The cores are optimized for the baseband-processing requirements in wireless standards. The M-rDSP architecture combines the power of a software-programmable, 32-bit RISC processor (mRISC) and an eight- to 64-cell reconfigurable cell array. Each reconfigurable cell contains an ALU, a MAC, and logic units, as well as specialized functional units that designers can use for wireless applications. The reconfigurable cell array can switch from one application-specific set of instructions to another in one clock cycle. For 3G wireless chip-rate processing, each reconfigurable cell contains a complex-correlator unit as a specialized functional unit.

Morpho has mapped optimized software-kernel libraries, based on various communication algorithms, into its M-rDSP core and provides reference-software applications that demonstrate communications protocols and standards. Morpho provides a fully synthesizable core, a C++ cycle-callable simulation model of the M-rDSP Core, synthesis scripts/test benches, a "C" compiler, a simulator (bit accurate/cycle accurate), a library of preoptimized kernels, debugging tools, and detailed documentation. It offers hardware-development systems and software tools that it bases on a proprietary software-tool chain that follows the most commonly used and understood tools in the market today.

The PNX1700, the newest member of Philip's Nexperia family of media processors, targets connected multimedia products, such as IP set-top boxes, digital-media adapters, personal video recorders, videophones, and televisions. In addition to having high-definition video capabilities, the PNX1700 connected media processor doubles the performance of previous generations, and maintains hardware and software compatibility. It features a 500-MHz, 32-bit, superpipelined TriMedia CPU core integrated with a TFT (thin-film-transistor) LCD controller, an Ethernet 10/100 MAC, and multimedia and floating-point instructions for image scaling, advanced deinterlacing, and 2-D graphics acceleration. The PNX1700 supports dynamic frequency and power management that enables designers to tailor power consumption to the application requirements.

Philip's Nexperia PNX5220 cellular multimedia baseband, with dual Adelante 16-bit RD16024 DSP cores and an ARM926 subsystem, targets feature-rich mobile handsets and smart-phone applications. It supports quadband 850-, 900-, 1800-, and 1900-MHz operation for GSM, GPRS, and EDGE and dual-band operation for UMTS. One DSP core handles the communication modem, and the other core performs the advanced audio features. Audio-processing support includes 64-voice stereo polyphony, enhanced AAC+ codecs, MP3 decoding, and wideband speech processing. Baseband-processing support includes a full software EDGE receiver and up to class 123 and SAIC (single-antenna interference cancellation). The Nexperia PNX5220 uses the 208-MHz ARM926 subsystem with hardware accelerators for application processing.

The PNX5220 memory architecture for the baseband processing uses multiple parallel buses to support NAND flash, SDRAM, cellular RAM, and burst-mode/page-mode memory. The ARM9 processor core uses a multilayer AHB structure to separate slow external peripherals from fast external memories to optimize the interaction with on- and off-chip memories. The PNX5220 has built-in Java acceleration and uses independent processing units as bus masters to enable the functional units to form a balanced network. The PNX5220 runs video at 30 frames/sec in CIF resolution and provides the hooks for GPS and other connectivity functions, such as WLAN and Bluetooth. It also allows the phone to connect via mobile connectivity standards, such as USB OTG (on the go) and fast IrDa.

The Philips' Adelante DSP technology includes the 16-bit RD1602x DSP core family and the 24-bit RD2412x DSP core family with a user-definable VLIW architecture. The RD16024 is the newest 16-bit programmable DSP core. The 24-bit Philips' Adelante RD24121 DSP core, with its 56-bit accumulator size, has an advanced instruction-set architecture suitable for audio applications requiring a high dynamic range. This architecture enables designers to trade between performance and operating voltage to enable lower power operation. The RD24121 includes an eight-stage pipeline with an orthogonal-register-file approach beneficial for the C compiler.

The Adelante software-development kit for multicore SOC architectures includes a graphical front-end with access to the underlying tool components, such as the compiler, assembler, linker, simulator, emulator, and profiler. It also offers a standard DSP firmware library with a set of DSP-related functions, such as FFT, FIR, and geometric functions. Philips makes available an FPGA-mapping of the DSP core and subsystem.

RC Module bases its NeuroMatrix NM6403 DSP family of dual-core application-specific DSP processors on the NeuroMatrix Core. It targets video-image processing, radio-navigation, and radar applications and provides scalable performance by employing a programmable operand width of 1 to 64 bits; this flexibility allows designers to trade precision for performance. The NM6403 processor includes a 32/64-bit RISC processor and a 1- to 64-bit vector coprocessor that supports vector operations with elements of variable bit lengths.

This year, RC Module introduced a new software-development kit for the NeuroMatrix NM6403 RISC/DSP processor. The NM-SDK Version 2.0 includes an optimizing C++ compiler (ISO/IEC 14882:1998 standard) and real-time DSP and video-image processing libraries. The compiler more closely adheres to the C++ standard, including templates, and uses the enhanced optimizing algorithms that allow increasing program execution speed and decreasing code size. The assembly language has an intuitive syntax and is close to high-level languages so it can simplify the development and understanding of source code for math-intensive real-time algorithms.

The MC2301 PCI digital-signal memory-evaluation board targets high-frequency analog-signal processing, complex high-frequency analog-signal generation, and DSP software/hardware prototyping and development. The MC2301 has one 1879BM3 DSM SOC, a 64-Mbyte SDRAM bank, analog input and output buffers, and a PCI-host interface. The shared memory is accessible for reading and writing both from the digital-signal memory chip and from the PCI bus. The MC2301 features a programmable 128-bit on-chip controller; a DSP core; 2-Mbit on-chip SRAM; two 600M-sample/sec, 6-bit ADC inputs; two 600M-sample/sec, 8-bit DAC outputs; and 64 Mbytes of onboard SDRAM.

Sensory's RSC family of devices performs recognition, speech synthesis, and general-purpose product control. The RSC line includes a 16-bit ADC, a 10-bit DAC, an alternative PWM output amplifier, 128 kbytes of on-chip ROM, 4 kbytes of on-chip RAM, comparators, timers, and general-purpose I/O. The RSC-4x provides on-chip integration of features, including a microphone preamplifier, twin-DMA units, vector accelerator, hardware multiplier, timers, and 4.8 kbytes of RAM. You can build a complete system with little more than a battery, a speaker, a microphone, and a few resistors and capacitors. Multiple ROM options are available.

Over the previous year, Sensory introduced FluentChip firmware, which enables higher accuracy, larger vocabularies, improved speech compression, better trigger-word detection and rejection, more noise tolerance, improved speaker-dependent recognition performance, and more instruments for music. The RSC line supports speaker-independent recognition, speaker-dependent recognition, speaker verification for voice biometric security, speech compression for speech playback (high-quality, 2400-bps compression), and music synthesis at no additional cost.

The RSC programming and debugging tools include the Phyton macro assembler, a C compiler, and an in-circuit emulator, all running in an integrated development environment. Hardware demonstration and evaluation boards are available for testing and prototyping. The speech tools include Sensory's QuickT2SI speaker-independent recognition-set development tools and QuickSynthesis speech compression for playback of voice files.

StarCore develops and licenses the StarCore processor architecture to OEMs and semiconductor suppliers as a family of fully synthesizable cores and subsystems. The StarCore subsystems provide scalable performance across a range of communication, wireless, and multimedia applications. They include a complete set of subsystem IP blocks, such as memory controllers, an interrupt controller, and an accelerator interface to reduce development time. The design is fully synthesizable, making it readily transferable from one foundry to another as market and product needs change.

StarCore has expanded the SC1000 instruction set to include video-processing instructions, improved code density, and enhanced RTOS support for mobile multimedia applications, such as smart phones, digital still cameras, and digital camcorders. StarCore also offers the SC2000 family, which is fully binary compatible with the SC1000 series of products, for video and portable multimedia. The two-MAC SC2200 and four-MAC SC2400 include dedicated video-processing instructions, additional RTOS support, improved code density, and improved power consumption. The SC2400 family of processors offers a 60% improvement in multimedia performance over the SC1400 family of processor products.

The SC2200 and SC2400 processor cores are available in synthesizable Verilog RTL. The SP2201 and SP2401 subsystems support embedded applications, featuring enhanced multimedia performance with on-chip emulation, memory interfaces, a DMA interface, an AHB-compliant system bus-interface, aclock-control unit, and an interrupt-control unit. The SP2202 and SP2402 subsystems support advanced applications, including all the features of the SP2201 and SP2401 subsystems, plus data- and program-cache controllers, a memory-protection unit, and a high-speed interface to connect application-specific accelerators.

StarCore has an ecosystem of companies that provide customer support, development tools, operating systems, and application software via the StarCore Alliance Program. The company also offers technical-support programs for licensees of its technology and for developers working on StarCore-based designs.

STMicroelectronics' new ST140 quad-MAC DSP core extends the ST122 dual-MAC implementation of the ST100 architecture that targets cellular-phone-infrastructure applications. The ST140 DSP is available as soft IP or hard macros, and it includes Viterbi-specific instructions and the ability to support user-defined operators. STMicroelectronics can map the core in various technologies and offers it with a full set of interfaces, peripherals, and memory IP. The architecture maintains software legacy between both cores and emphasizes the C ST100 compiler technology to benefit from a high level of processing parallelism directly from C source code.

The development environment supports modeling, profiling, optimizing, and debugging for any ST140-based application, including multicore designs. The STMicroelectronics technical-support team provides on-site training and brings day-to-day dedicated support to customers.

Tensilica's configurable, extensible, and synthesizable Xtensa LX processor core enables designers using the Tensilica processor-generator tool to build Xtensa LX processors that exactly fit the target task. The designer selects and configures predefined processor attributes and, by using TIEs (Tensilica Instruction Extensions), adds Verilog descriptions of execution datapaths, I/O ports, and registers that can deliver performance, area, and power characteristics equivalent to custom-logic design. Over the previous year, Tensilica introduced the Xpres compiler, which can analyze the designer's C/C++ code and automatically suggest and generate the TIE instructions to optimize the processor for the application.

Tensilica's Xtensa LX processor core with Vectra DSP engine supports wide datapaths and traditional DSP tasks. The system can deliver RTL-equivalent I/O through a ports- and queues-mechanism that directly connects to the processor's execution unit to bypass the load/store operation. The Vectra LX DSP engine takes advantage of the Flix architecture and uses 64-bit instruction words containing three issue slots for ALU, MAC, and load/store operations. Tensilica offers Web-based design support and an FPGA-based development board and can customize the Vectra LX DSP engine on a consulting basis.

Texas Instruments' 90-nm, 1-GHz TMS320C6414T, C6415T, and C6416T DSPs target audio, speech, video, and imaging applications. Also new is a 720-MHz version of the TMS320DM642 DSP-based digital-media processor targeting consumer electronics and set-top boxes. The DM642 delivers high-definition video streams in Microsoft's WMV HD (Windows Media Video high-definition) at 720-pixel resolution and processes standard-definition video decoding for the H.264 format. The new TMS320R2811 and R2812 digital-signal controllers target industrial, automotive, sensing, flow metering, and e-metering applications by providing 20k words of on-chip SRAM and allowing developers to add unlimited external memory to their designs via the SPI port. They include an integrated high-speed, multichannel, 12-bit ADC to measure system parameters and respond quickly to meet the input- and output-intensive requirements specific to applications such as precision e-meters and flow meters.

The TMS320C6000 DSP platform comprises the TMS-320C64x, TMS320DM64x and TMS320C62x fixed-point generations as well as the TMS320C67x floating-point generation. The C64x generation of high-performance DSPs targets broadband and video infrastructure as well as video and imaging applications. The DM64x generation of programmable DSP-based media processors targets streaming and multimedia applications. The C62x fixed-point family targets multichannel, multifunction applications; the C67x floating-point DSP generation targets home audio, industrial automation, voice and speech recognition, as well as high-end graphics and imaging.

The TMS320C5000 DSP platform comprises the TMS320C54x and TMS320C55x fixed-point generations. The C54x generation consists of more than 17 code-compatible devices covering a range of performance and peripheral options, as well as low-power operation. The TMS320C55x generation includes power-efficient DSPs. The new TMS320C5503, TMS320C5507, and TMS320C5509A DSPs offer a combination of performance, memory, peripherals, and low power, targeting mobile, portable, and other low-power, real-time-signal-processing applications. These devices feature standby power at 0.12 mW. The new TMS320C5405, a 16-bit, fixed-point DSP available in a 7×7-mm package targets systems emphasizing small size, low power consumption, and lower cost.

Texas instruments also released the C5000 Low-Power Design Tools within the eXpressDSP tools. The design-tool suite includes power-planning tools to create trial configurations and determine the net power consumption; power-management routines within the DSP/BIOS to automatically implement power saving strategies at the operating-system level; a power-scaling library to implement power scaling through dynamic control of the runtime core frequency and voltage; and integration with National Instruments' application power-measurement tools to help designers visually measure and analyze power in their systems.

Texas Instruments' TMS320C2000 digital-signal controllers combine DSP technology with microcontroller-peripheral integration. The TMS320C28x generation includes 32-bit DSP-based controllers with onboard flash memory or ROM and offers performance to 150 MIPS for control algorithms in real time, such as sensorless speed control, random PWM, and power-factor correction supporting control-, automotive-, and industrial-motor applications. The TMS320C24x generation offers 20 to 40 MIPS of DSP performance with integrated flash memory or ROM and targets control algorithms in cost-sensitive and space-constrained applications, such as consumer white goods.

Texas Instruments offers DSP starter kits and evaluation modules accompanied with the Code Composer Studio integrated development environment, the DSP/BIOS real-time kernel, application-specific algorithms, application demos, and getting-started reference frameworks. Designers can visit its Web site for technical support, online training, and access to the KnowledgeBase and technical documentation. The company offers one- and four-day workshops worldwide for hands-on instructions.

Texas Instruments and Ateme jointly announced the availability of the NVDK (Network Video Development Kit), which they base on the TMS320C64x 1-GHz DSP. The NVDK, designed by Ateme, is a development platform for the creation of broadcast head-end and advanced digital-media and video applications, such as video infrastructure, that require superior processing performance and streaming features. It includes foundation software for developing imaging and video applications as well as an Ethernet daughtercard, an audio/video-interface box, drivers for a PCI board-support library, and an H.264 decoder evaluation tool.

Texas Instruments and Wintech Digital Systems now offer the VDP (Videophone Development Platform) for designing point-to-point IP-based videophone systems using the 600-MHz DSP-based TMS320DM643 digital-media processor. The VDP can enable OEMs to quickly enter this market with videophones that support H.264 as well as perform video encoding and decoding on a single chip. The VDP includes two videophones with an LCD and camera subsystem, a power supply and connectivity interface, Ethernet support, audio and video codecs, and communication stacks.

The soft-IP-core, fixed-point DSP family, bus controller, peripherals, and microprocessor interfaces from 3DSP use a scalable 32-bit SuperSIMD architecture. The core supports multiprocessor systems, program cache or direct-mapped program memory, prioritized interrupts, and a JTAG-only debugging interface. The 3DSP core supports two SIMD multiplier options. The first option is a dual 24×16-bit multiplier that can perform two 24×16-bit multiplies, four 16×16-bit multiplies, or eight 8×16-bit multiplies in a single cycle. The second option is a dual 32×32-bit multiplier that can perform all the functions of the 24×16-multiplier and two 32×32-bit multiplies in one cycle.

The programmable, five-stage-pipelined DSP SP-3 core targets MP3-player, home-audio (AAC, AC3), wireless-GSM-phone, GPS, and CPE (customer-premises-equipment) VOP (voice-over-packet)-processing applications. The programmable, superscalar, dual-issue, five-stage-pipelined SP-5 core DSP targets 3G wireless, VOIP gateway, xDSL, MPEG2, MPEG4, and wireless-LAN applications. The programmable, dual-mode, nine-stage-pipelined SP-20/UniPHY DSP-IP core targets multimedia applications including multimedia over wireless. The "soft-datapath" technology and programmability enable a "softPHY" implementation that facilitates modification for changing physical-layer standards.

Xilinx supplies programmable-logic devices, design tools, algorithms, and services. The Virtex-4 family of FPGAs delivers as many as 512 500-MHz XtremeDSP slices that target high-performance applications, such as digital radios and baseband cards for narrowband, spread-spectrum, multicarrier communication systems, and high-performance video- and image-processing systems. The lower cost Spartan-3 family of FPGAs targets high-volume applications, such as multimedia boxes and displays.

Xilinx and its partners support Xilinx XtremeDSP, which includes more than 100 algorithms, and the System Generator for DSP tool, which enables designers to build sophisticated systems including Matlab, Simulink, and HDL models. System Generator allows designers to automatically generate FPGA bit streams and supports high-bandwidth hardware in the loop for system verification.