News and New Products

Processor and tools support dynamic reconfiguration

By Robert Cravotta -- EDN, 5/26/2005

Dynamically reconfigurable silicon-sharing enables designers to implement a design with a smaller processor and possibly with lower power consumption than a fixed-function processor device. Atmel’s FPSLIC (field-programmable system-level IC) II combines an 8-bit AVR processor core with an on-chip SRAM-based FPGA that enables multiple interfaces, peripherals, and coprocessors to share the same FPGA silicon at different times during application operation (Picture). Atmel’s Reconfiguration Designer and Temporal Designer back-end EDA tools automate the implementation, timing, and control of the silicon-sharing process.

The SRAM-based FPGA has not been the main obstacle to supporting dynamic silicon-sharing; rather, before the availability of these tools, designers would need to manually ensure that they had loaded the correct function into the FPGA at the correct time and that functions did not incorrectly load atop each other. The FPSLIC II employs a configuration controller, two DMA controllers, a dedicated FPGA-to-AVR interface, and a “virtual socket” in the FPGA portion of the programmable SOC (system on chip) to enable the tools to automate reconfiguring the FPGA. Libraries containing previously designed peripherals, interfaces, and coprocessors load into the virtual socket to populate the FPGA. The FPSLIC II consumes 50 ìA in standby and 2 to 3 mA/MHz during operation.

Atmel provides a library of reference designs that includes Ethernet, memory, SPI, secure digital I/O, a multimedia card, DMA, speech synthesis, ADPCM (adaptive differential-pulse-code modulation), audio-codec interfaces, and DES (Data Encryption Standard)/triple-DES algorithms. FPSLIC II family devices are available now at prices ranging from $5 to $15 (10,000) and FPGA densities of 256 to 2300 core cells in lead-free, 144-pin TQFP and 256-ball BGA packages.

Atmel, 1-408-441-0311, www.atmel.com.