Reliable sign-off at smaller nodes

The demand for more functions and better performance continues to fuel the drive to more advanced process technologies. With each new technology generation, however, designers must deal with an increasing array of electrical and physical effects that impact device performance. For earlier process technologies, conventional timing-sign-off methods could safely rely on approximations, such as gross estimates for parasitics, simple load models, or even the use of a single overall derating factor for supply voltage. At technology nodes of 130 nm and less, however, IR drop and signal-integrity problems in complex designs can induce critical-path timing violations and even silicon failure. These nanometer effects invalidate approximations in conventional timing analysis, opening a significant gap between predicted performance and silicon results.

As a result, semiconductor companies see multiple design iterations and silicon re-spins as design teams struggle to achieve reliable timing closure with conventional methods. Facing emerging requirements for increased accuracy in nanometer analysis, designers need an integrated subflow that reliably accounts for power and signal-integrity effects in nanometer timing sign-off. At the heart of this subflow, sophisticated delay-calculation methods use instance-specific operating voltages, dynamic load models, and accurate parasitic data that reliably account for advanced manufacturing effects associated with copper processing, metal fill, and wire slotting.

For CMOS designs, increasing density and shrinking process technologies mean significantly greater leakage current—a major problem, because leakage current means continued power dissipation even when a circuit is in idle mode. Power dissipation due to leakage current accounts for an increasing share of overall power dissipation with each technology node (Figure 1). However, for a typical CMOS SOC (system-on-chip) device, dynamic power dissipation remains the dominant contributor to overall power consumption. The following equation expresses dynamic, or switching, power (P_D):

where k is the toggle rate, C_L is the total capacitance that needs to charged or discharged, V is the supply voltage, and f_CLK is the switching frequency.

Because dynamic power rises as the square of supply voltage, a common strategy for reducing power involves reducing supply voltage. Yet, lower supply voltage results in lower noise margins, causing a corresponding increase in a design's sensitivity to signal-integrity problems, such as crosstalk. In turn, crosstalk glitches propagate to latches in signal paths, creating functional failures. In nanometer designs, IR drop caused by resistance in extensive power nets affects timing and further increases signal-integrity problems. At the same time, the continued drive to higher clock rates in advanced devices increases not only dynamic power, but also parasitic effects, producing a potentially fatal combination of IR drop and signal-integrity problems, impacting circuit timing and function. Indeed, IR drop and signal-integrity problems are responsible for a major share of silicon failures in advanced designs (Figure 2).

Conventional timing-sign-off approaches are inadequate for nanometer technologies, because the combination of IR-drop and signal-integrity problems introduces timing problems that invalidate traditional delay calculations that conventional timing analysis uses. For reliable nanometer timing analysis, engineers need to account for coupling between nets, not just coupling to ground, and they need to include interactions between IR drop and signal integrity on timing.

Because of the growing impact of these nanometer effects on critical timing, designers using conventional timing-analysis methods find that their analyses fail to predict actual silicon performance. As a result, only slightly more than 40% of nanometer designs operate as expected, and more than 60% need a complete mask re-spin to achieve acceptable yield and performance (Figure 3).

Worse, the insidious nature of these nanometer effects can cause failures only under certain operating conditions, process corners, or temperatures. Consequently, these problems are typically hard to isolate, and designers often consider them yield problems, when in fact they relate directly to crosstalk or IR-drop problems. For example, a high-performance design that operates perfectly at 1.2V could fail at 0.9V, because susceptibility to crosstalk increases due to the lower noise margins at these lower levels. Silicon failure can also arise during otherwise-normal operation if small glitches occur simultaneously—for example, combining nonlinearly to produce a much larger glitch and, ultimately, a functional violation at a latch or flip-flop.

Traditionally, engineers have been able to protect their designs from various sources of timing variations by widening margins in timing and in physical layout. At advanced technology nodes, however, the impact of nanometer effects can exceed reasonable margins, resulting in failed silicon and costly diagnostic efforts to identify the root causes of failures. Applying margins across an entire design is costly in design time and final results. Increased timing margins force the design to meet timing at higher clock rates, requiring larger buffers to drive signals faster, thus increasing power consumption. This approach can actually lengthen the design cycle and lead to the use of larger buffers, more power dissipation and heat, greater risk of signal-integrity and electromigration problems, and increased chip area. The impact of this approach even affects the design team as a whole, often requiring long ECO (engineering-change-order) runs, increased work to fix paths that do not actually need fixing, and tape-out delays. Without detailed analysis, designers may build in margins at the wrong place in a design and expend efforts optimizing the wrong timing paths.

Ultimately, even the use of reasonably sized margins in timing cannot offset the impact of IR-drop and signal-integrity effects, and traditional analysis methods have proved inadequate to account for these problems. For example, conventional power-analysis methods have typically relied on a single derating factor to determine IR-drop effects in a design. Engineers often derate global drain-to-drain voltage by 2 to 5% and rerun the delay calculation, but this approach applies the same supply voltage to all instances in a design and typically provides an overoptimistic view of results. In fact, the impact of IR drop on timing is nonlinear with supply voltage. As a result, the use of static-timing analysis with simple linear derated power cannot correctly identify setup-and-hold-time violations that IR-drop-related delay variations cause.

In some cases, engineers facing timing violations might overlook IR-drop problems, assuming that IR drop will result only in setup-timing violations. In fact, IR-drop and signal-integrity problems can result in not only setup violations—when IR drop and signal integrity slow signal transitions in victim nets—but also hold-time violations when these effects slow clock edges (Figure 4). Slower clock edges mean data will arrive too early, resulting in a hold problem. Furthermore, most engineers assume that IR drop results in slower edges, but it can also speed signal transitions if a signal is not sitting at full drain-to-drain voltage, requiring less time to discharge to ground. For engineers left with poorly performing silicon, the accumulation of timing problems caused by IR drop and signal integrity can be difficult at best to isolate late in the development process.

Even separately analyzing IR-drop or signal-integrity effects can leave designs vulnerable to failure, particularly at 90 nm and smaller. IR drop affects timing, which affects signal integrity. In turn, increased signal-integrity problems can cause further timing effects. For example, the width and height of a timing-affecting noise pulse can shift with IR drop, which can also directly increase the chance that the glitch propagates through logic gates (Figure 5). In fact, switching power, IR drop, timing, and signal integrity all have a complex relationship in affecting timing.

The interaction between IR drop and signal integrity will become more important as designers move to 90-nm and smaller processes. The likelihood of crosstalk and IR drop each increase nonlinearly with every generation of technology—combining for an overall exponential increase at next-generation process nodes. As designers address increasing power concerns with more sophisticated low-power-design methods, this combination of higher power, lower voltage, higher clock frequency, and denser wiring increases the likelihood that dynamic IR drop and crosstalk effects will cause timing and functional failures in silicon. Because of the relationship between these factors, reliable sign-off analysis for nanometer designs requires an integrated subflow that can simultaneously calculate these effects.

Nanometer-design timing analysis requires a comprehensive subflow that accounts for the interactions of IR-drop and signal-integrity effects on timing, based on accurate parasitic data and detailed models. Tools such as Voltage Storm, CeltIC NDC, and Fire & Ice QX combine accurate parasitic extraction, advanced models, and simultaneous analysis of the effects of IR drop and signal integrity on timing before tape-out.

Accurate parasitic extraction is essential for this type of comprehensive analysis for providing the detailed data for timing analysis in nanometer designs. Accurate parasitic extraction is critical for advanced copper-based manufacturing processes, which introduce performance variations in individual wires. Because copper is softer than the surrounding dielectric, CMP (chemical mechanical polishing) can result in wires with uneven copper thickness across a chip, so even wires of equal length can exhibit variable parasitic delay, causing actual silicon performance to diverge from expected timing behavior. Manufacturers insert dummy metal to increase copper uniformity across a chip and decrease CMP effects. Yet, the metal fill itself changes the coupling capacitance between the wires, and extracted parasitic values must accurately reflect its impact.

In advanced nanometer designs, the resistance of a wire depends on its individual characteristics, such as width and distance from neighboring wires. To account for these factors, advanced extraction incorporates precise 3-D modeling and characterization of advanced dielectrics, trapezoidal conductors, copper technology, and other modern process technologies. These more accurate extraction methods can account for copper-process effects—such as CMP erosion, metal fill, and wire-edge enlargement—and provide the accurate coupling capacitance necessary for reliable signal-integrity analysis.

With Cadence's integrated tool set, Fire & Ice QX provides detailed parasitic extraction, and VoltageStorm performs power-rail analysis. The system automatically feeds the Fire &Ice QX output and the instance-specific operating voltages from VoltageStorm power analysis to the CeltIC NDC delay-calculation engine, which can simultaneously account for the effect of IR drop and signal integrity on timing and performance. Along with this design data, accurate delay calculation requires detailed models that can provide accurate timing analysis at all required process, voltage, and temperature points. As a result, designers need fully characterized IP (intellectual-property) models and libraries fully recalibrated based on realistic parameters that the foundry provides. For example, conventional delay calculators and timing-analysis engines support accurate delay calculation for only a single nominal voltage level. The use of other voltage values introduces an error due to linear derating that often exceeds 20% from Spice, particularly for slower, low-power cells.

Traditional delay calculators face interpolation errors even if they can use timing views for all required voltage levels. For example, this situation can occur due to IR drop that simultaneous switching of I/Os, clocks, and on-chip devices causes. Traditional delay models, including table- and polynomial-based models, model the driver as a voltage source. To accurately model cell delays for varying voltage levels, you must characterize these types of models in a lengthy process. For example, using six voltage levels at three process or temperature corners requires 18 timing-library characterizations.

Hence, to support more comprehensive analysis, IP vendors are providing more accurate libraries using ECSMs (effective current-source models). Nonlinear ECSM-delay models use characterized measurements of current and voltage (I/V curves) over multiple time intervals with combinations of input-slew and output-loading capacitance (Figure 6). ECSM I/V curves are the bases for a more accurate output-driver model, in which each driver is represented as a voltage-controlled current source. Using the drive current, ECSM can determine voltages by simulating the drive of RC networks. In turn, drive voltages and receiving voltages generate timing parameters of the RC networks. Also, ECSM enables accurate modeling of the impact of changing load capacitance. As you apply a voltage to the gate of a device, ECSMs faithfully reflect actual device-capacitance changes—a capability unavailable with earlier analysis methods. As a result, the Cadence integrated delay calculator can now use this instance-level detail to more accurately calculate path delays by including the nonlinear effects of both IR-drop and signal-integrity problems (Figure 7).

Because ECSMs contain both current and voltage information, they are useful for modeling the impact of voltage variation on delay without requiring characterized data for every potential supply and can still closely match transistor behavior. A recent study produced a methodology for performing voltage-variation-aware delay calculation (Reference 1). It demonstrates that with ECSM data characterized at only three operating voltages, accurate delay calculation is possible across a wider range of operating voltages (Figure 8).

Cadence's flow also incorporates capabilities for employing both static and dynamic analysis. Designers use static IR-drop analysis to identify global power-routing issues, such as open circuits, insufficient routing widths, lack of power straps, missing vias, and missing via arrays. Static analysis is also the preferred approach for power-electromigration verification, because it reliably reveals the results of a design operating over an extended period of time. In contrast, dynamic analysis reports IR-drop transients on the power networks, typically caused by localized simultaneous switching of devices. Advanced tools can report the density and efficiency of decoupling capacitors in a nanometer design. With these results, designers can identify where to optimize decoupling capacitance to reduce IR-drop transients or leakage.

In fact, due to the high-power-rail parasitic capacitance and the capacitance associated with nonswitching logic, static analysis is sufficient for most designs as small as 130 nm. Indeed, using dynamic analysis without previous static analysis is like fine-tuning a car engine that is missing a spark plug: You can do it, but you should first handle the more fundamental work of replacing the missing part. Static analysis provides engineers with a tool to identify gross violations and ensure the general robustness of the power rail. After this fundamental analysis, dynamic analysis helps engineers optimize the number and placement of decoupling capacitors necessary to eliminate glitches, rather than add unnecessary decoupling capacitances that serve only to increase leakage current and overall power consumption.

As semiconductor manufacturers move to advanced nanometer process technologies at 130 nm and smaller, IR-drop and signal-integrity problems can combine to introduce timing violations and produce functional failures in silicon. Conventional timing-analysis methods, designed for earlier process generations, lack the ability to account for these nanometer effects, leading to a growing disparity between simulated results and silicon performance.

To achieve reliable timing closure in nanometer designs, engineers need more accurate methods that account for the growing impact of IR-drop and signal-integrity problems on timing and performance. New integrated subflows supported by advanced tool sets combine parasitic extraction, instance-specific models, and simultaneous analysis of IR drop and signal integrity necessary to uncover subtle timing and functional flaws in nanometer designs. As designers move to more complex, low-power SOC designs, such an integrated subflow will become increasingly essential for reliable design sign-off at nanometer process nodes.