News and New Products

FROM EDN EUROPE: Big-chip synthesis tools move on

by Graham Prophet -- EDN Europe, 5/12/2005

For designers of large system-on-chip ICs, Synopsys has introduced the latest evolutionary step in its synthesis tool sequence. From the original Design Compiler, the company moved to physical synthesis and now offers Galaxy IC Compiler. This tool upgrades and consolidates the functions that were previously carried out by Physical Compiler, Astro (optimisation, place and route) Jupiter XT (floorplanning) and some power analysis tools. Using a common database and greater concurrency in the physical synthesis process, the new suite handles physical synthesis, clock tree synthesis, routing, yield optimisation and sign-off correlation concurrently. A key building block is XPS (extended physical synthesis), meaning that the physical synthesis process covers more of the place, route and clock design cycle.

Users can obtain faster results and better convergence, Synopsys says, because during placement, the tool better anticipates how the router will do its job (although the company is reticent about exactly how this anticipation is effected) and adjusts placement accordingly. Concurrent design encompasses clock tree synthesis to a greater extent than was previously possible. There is also an increased focus on the design process being Sign-off-driven, that is, the optimisation process takes account of more final sign-off objectives, across a wider spread of process variables.

Given the availability of yield-characterised libraries, yield optimisation can also be one of the drivers for the design process. The company says that results from lead customers' evaluations of the tool package confirm gains in yield, area and power, when used on designs built in 130, 90 and 65 nm technologies. A full licence for the package will cost $735,000 for one year, which is, Synopsys says, about the same as the consolidated price of the packages it replaces.

Synopsys, +44 1189 313822, www.synopsys.com