Feature

Multiprotocol transceivers perform feats of champions

With the abundance of PDAs, laptops, printers and scanners, routers and servers, e-mail, and spammers, the amount of data we access daily staggers the imagination. But it doesn't happen by magic. Somehow those gigabits of data must get from here to there, and before the job is done, they must be in a format compatible with gear built yesterday or more than a decade ago. No problem.

By Joshua Israelsohn, Technical Editor -- EDN, 11/23/2000

On the whole, we humans are a chatty lot—an attribute we tend to pass on readily. We make gadgets that talk to other gadgets, engendering formal and casual networks of distributed data sources and processing ware and enabling rapid and inexpensive access to voluminous data. As with humans, there's no single, universally adopted method for electronically transferring information from one machine to another and for many of the same reasons; some are due to the distinctive strengths and weaknesses among available choices, but others are due to historical factors or application-centric preferences. The challenges for I/O designers is to create an inexpensive, robust interface compatible with standards and technologies that have endured and evolved for more than 30 years.

At the physical layer, machines use a variety of mutually incompatible signaling conventions. You can find standards specifying signal levels, data rates, circuit topologies, media, and connector geometries in many combinations (Figure 1). The proliferation of interface standards often forces OEMs to offer different versions of a product for each supported standard. The result is a limitation on economies of scale without adding value perceivable to differentiated end users. Even when the I/O function is isolated to a plug-in card, manufacturers bear or pass on the stocking, configuring, and tracking costs.

Wiring cost, a significant factor in data-communications hardware budgets, can prevent end users from adopting unified designs. Limitations on signaling distance at a given data rate may force end users to choose one interface standard for areas with tightly clustered data sources and destinations and select a different standard for configurations that are distributed over a larger area (Reference 1). In cases where you need the same function in both areas, end users bear costs for stocking spares and for configuring and tracking hardware; these expenses add to the total cost of ownership.

Multiprotocol transceivers offer one solution to the compatibility problem. These devices adapt on command to one of several interface standards—binary babelfish, so to speak (Reference 2). Such devices adapt to the various topological, signal-level, and termination requirements of the selected standard (see sidebar, "RS 101"). Of the I/O chip manufacturers selling into the market for devices running at 10 Mbps and slower, several have developed lines of multiprotocol devices (Table 1). Each manufacturer's product line has distinguished capabilities and useful functional overlap with other product lines. You should carefully examine each transceiver before you decide which is best for your application.

Integration or disintegration

Since Robert Noyce and Jack Kilby started us down the IC road 41 years ago, denser integration has almost always been better. Under the SOC banner, digital-chip makers continue to push toward greater levels of integration to the benefit of and wonderment of many. Analog-IC manufacturers, however, know the benefits of offering functions at various levels of integration. Even in products whose content is overwhelmingly digital, OEM designers need the flexibility to carefully place and route power supply, clock generation, and I/O components if they expect to realize the full parametric performance of these parts.

Several factors might influence your choice of integration level for multiprotocol transceivers. First, not all implementations support all signals that physical-layer standards define. For example, most current laptop and desktop computers present an EIA232 port through a DB-9 rather than a DB-25 connector. The smaller, less expensive connector supports two data lines, six status and flow-control lines, and ground. In cases where status detection is unnecessary and software flow control is acceptable, the minimal 232 interface requires only two signals and a ground. You most likely cannot support numerous protocols starting with a minimal implementation of 232, but few applications require 20 defined signals. Another example, V.35, defines 14 signals, half of which process optional signals. For multiprotocols that require you to support only a handful of signals, transceivers at the lower end of the integration range can save you money, space, and power.

Splitting a function between the sides of a pc board or squeezing a function into an odd-sized space is a challenge if the entire function is integrated in one large chip. Of the signals you need to support, only data and clock run at the full data rate. Drivers with slower edge rates can often transmit control and status signals that convey sparser information. Particularly in dense products where room for I/O is already at a premium, you may want to take advantage of the placement flexibility that lower integration offers. This arrangement allows you to process data and clock signals in one small transceiver package placed close to the I/O connector, for example. At the same time, you can tuck a second small transceiver package that carries status and control signals where it best fits in your mechanical design.

Examples of parts on the lower end of the integration scale include Linear Technology's LTC154x and Maxim's MAX317x families. Depending on the communications standards and data rates you choose to support, you can also take advantage of programmable termination networks that both families offer, such as the LTC1344A, MAX3172, and MAX3174. The terminators read the protocol control and DCE/DTE select lines that manage the transceivers and configure themselves to present the correct impedance and topology to the I/O signal lines.

The flip side of the coin is that more highly integrated devices can save you from extensive external wiring in cases where you need to more fully support multiple interface standards. In such cases, the LTC154x and MAX317x families require three chips, including the terminator and a 4-bit control bus. The exception is Linear Technology's LTC1546, which brings the terminator on-chip and reduces the chip count from three to two.

Sipex has taken the higher integration road with its SP50x series of multiprotocol transceivers. These parts include seven drivers and seven receivers (eight each for the SP508), an on-chip charge pump, and an on-chip programmable termination network. These more highly integrated parts can also offer features that are difficult to realize otherwise. For example, a built-in loop-back mode in SP50x transceivers allows you to run self-test routines to check I/O functions without disturbing the I/O connector. Systems can use this feature as part of their initialization routines or as part of separate diagnostics.

Just as a lower level of integration allows for placement flexibility, having the whole interface under one roof makes routing simpler. The SP508, the largest of the Sipex chips in a 100-lead LQFP, measures 256 mm² lead-tip to lead-tip. The closest equivalent functions from the Linear Technology and Maxim families range from about 145 to 250 mm² for the chip set. This area excludes space required for additional routing and typically three additional bypass capacitors. All other things being equal (and they're not), the trade-off is the placement rigidity of one component, with the advantage of simple point-to-point wiring, versus the placement flexibility of the multichip interface, with more passives and complex routing. You should consider the amount and shape of available space, integrated features, and procurement and placement costs of I/O components before you decide which approach is best for your design.

Let's get physical

If your only challenge was to conjure an electrical interface to comply with the most popular standards, you could roll the credits and move on. But there's more to the physical layer than voltage levels and circuit topologies. Each I/O standard defines its own mechanical interface for DTE and DCE and calls out the connector geometry, gender, and pin-out (Figure 2). If you use multiprotocol transceivers to simplify the electrical interface, you need a strategy to mechanically attach the interface to protocol-specific nodes.

One common approach involves protocol-specific-interface cables that connect to a protocol-agnostic back-panel connector. The low-density version usually uses a DB-25 connector, which has enough pins to accommodate most popular standards. The advantage of this approach is that it uses a common, low-cost, readily available connector that EIA232 and EIA530 standards make use of directly. OEMs that choose this method need only supply-interface cables to support other protocols. The downside of this arrangement is that individual pins must support different signaling standards. At minimum, this scheme requires that unused (but still connected) differential driver outputs have reasonable tristate leakage specifications when they face a single-ended driver output. These outputs face voltages as large as ±25V; though in practice, signals rarely exceed ±12V.

Another choice, a high-density connector, allows for more flexible pin assignments. For example, OEM designers can segregate differential and single-ended signals, which eliminates the concern about stand-off voltage and tristate leakage performance over the full range of operating conditions. High-density connectors offer an additional advantage: You can use jumpers to code an interface type onto extra pins. The system can read these pins to detect and identify the protocol appropriate to the connected hardware when users attach the interface cable to a multiprotocol port (Figure 3). Most multiprotocol transceivers provide pullups on the mode select inputs to simplify this arrangement.

Depending on the type of device you design, you may choose to wire your interface as DTE, DCE, or switchable. Supplying an appropriately wired interface cable simplifies the task of integrating your equipment into the system.

Shaking hands with the unknown

Unlike most components in your product, I/O devices reach out into an electrical environment that is well-defined under normal operating conditions but only loosely defined under anticipated abnormal conditions. Transceivers can be connected to the expected network, open circuits, short circuits, or a scrambled connection.

Meanwhile, end users who are responsible for networks, small or large, private or public, want some assurance that your product cannot to bring their network down under any conditions. For example, two pieces of equipment connected by a long wire cannot depend on a specific power-up sequence. I/O circuits must behave predictably when they are unpowered or connected to unpowered circuits. Miswired interfaces, although unfortunate, are predictable. Net1/Net2 certification ensures that transceivers behave predictably over normal and specified abnormal conditions. When you use Net1/Net2 compliant transceivers, you pass on these assurances to your customer.

Installers of datacomm routers and switchers often fail to take adequate precautions to prevent ESD strikes to I/O ports. Consumer equipment, such as digital cameras, PDAs, and laptop computers, are at risk of an ESD event with every use. Many system designers use TVSs on I/O lines as a matter of course, though multiprotocol transceivers are appearing with on-chip ESD protection that has the potential to save board space and assembly costs. However, ESD protection is not an absolute. You should evaluate a part's robustness in light of your product's anticipated operating environment. In your evaluation, you should pay particular attention to ESD strike voltage, incidence rate, and source.

If your transceivers have insufficient ESD ratings for their anticipated operating environments, you should select a TVS with a sufficiently high-energy rating and add its capacitance to your load budget. High-speed-data lines have limited tolerance for excess load capacitance before signal-integrity problems arise. Ironically, as manufacturers lower suppressors' trip voltages to adapt to lower voltage-signaling standards, they must increase the devices' doping concentration, which causes an exponential increase in the junction capacitance. Increasing the current-handling capacity, a consideration likely to experience repeated exposure to large ESD events, requires an increase in the junction area; this situation can result in an increase in the junction capacitance (Reference 3).

TVSs for datacomm applications are constructed to minimize their capacitance for a given trip voltage and current rating. They perform this task by connecting a suitably dimensioned junction diode in series with the suppressor diode (Reference 4). For example, you couldn't use a 500-pF suppressor on any but the slowest datacomm links. The series combination of that same suppressor with a 15 pF junction diode, however, reduces the total capacitance to 14.6 pF. Even a pair of these hybrid suppressors that are wired in antiparallel for bidirectional protection adds less than 30 pF to a node, which is reasonable for data lines to about 10 Mbps.

Some multiprotocol transceivers can operate at higher data rates than the historical maximums for supported standards. For example, SP508's six differential drivers can transmit at speeds as high as 40 Mbps. The tranceiver's two single-ended drivers operate as fast as 120 kbps. If you want to use these speeds, you need to choose transceivers with adequate on-chip ESD protection or budget your TVS and cable capacitances accordingly.

Author info

Contact Technical Editor Joshua Israelsohn at 1-617-558-4427, fax 1-617-558-4470, e-mail jisraelsohn@cahners.com.

Kishani, Aziz, Sipex Corp, Sept 29, 2000.