FPGA heavyweights get serious about hybrids

-- EDN, 11/23/2000

After years of insisting that large-scale logic integration was best accomplished in programmable gates, Altera and Xilinx have done an about-face. Heading down the path blazed by their smaller, more nimble competitors, such as Atmel (www.atmel.com), Lucent Technologies (www.lucent.com), and QuickLogic (www.quicklogic.com), the two leading programmable-logic suppliers are now embracing the concept of ASIC-plus-FPGA hybrids, and both companies are well along the path to first silicon sampling (see "The best (or worst?) of both worlds," EDN, Nov 11, 1999, pg 139 and "The end of the road?" EDN, May 13, 1999, pg 54).

Altera this summer announced its Excalibur program, initially targeting the Apex 20K programmable-logic family and consisting of the Nios processor soft core and both ARM (www.arm.com) and MIPS (www.mips.com) hard cores. The company chose late September's Embedded Systems Conference as the forum for unveiling additional details of the ARM and MIPS products. Altera's XA10 integrates a 200-MHz ARM922 core, including 8 kbytes each of instruction and data cache; 256 kbytes of dual-port SRAM; and 128 kbytes of single-port SRAM. The device will be available for sampling by year-end and will enter volume production in the first quarter of 2001. Altera plans to also embed the UART, interrupt controller, SDRAM controller, and timer/counter functions in an on-chip ASIC. The company will offer a plethora of additional peripherals as soft cores housed in programmable logic, all interconnected via multiple AMBA (ARM's Advanced Microcontroller Bus Architecture) buses, the same interconnection scheme that Lucent plans to use with its hybrids.

Close behind the XA10 will be the XM10, Altera's first MIPS-based hybrid chip. Specifically, Altera chose the 200-MHz MIPS32 4Kc core with 16 kbytes of instruction cache and 16 kbytes of data cache; single- and dual-port SRAM; and a single-cycle, 32x16-bit multiply-accumulator. Both ARM- and MIPS-based architectures will also come in smaller variants with less single- and dual-port RAM and programmable logic by midyear 2001, according to the company. And Altera has resurrected its MPLD (mask-programmable logic-device) program to provide lower cost, high-volume production variants of most of the devices. Table 1 shows planned ARM device features, and Table 2 shows end-of-2001 prices.

And what about Xilinx? The company isn't ready to talk product specifics yet, including when its first PowerPC-based hybrid chip will appear. But Xilinx will base the chip on the Virtex-II FPGA architecture, which the company indicates is still on track to achieve first silicon status before the end of this year. Xilinx has licensed both IBM's PowerPC core and CoreConnect bus technology. Virtex-II features developed with ASIC hybridization in mind include Active Interconnect buffering, which debuted on Virtex but which the company has now extended to all routing segments regardless of their length, and a tile-based architecture amenable to quick-turnaround mixing and matching of varying ASIC and FPGA proportions. Other pieces of the puzzle now in place include Xilinx's acquisition of RocketChips, a developer of high-speed serial-transceiver technologies, its licensing of Conexant's (www.conexant.com) SkyRail 3.125 Gbps protocol, and its acquisition of LavaLogic and the company's C and Java-based synthesis technology.

Altera, 1-408-544-7000, www.altera.com. at www.rscahners.ims.ca/ednmag.

Xilinx, 1-408-559-7778, www.xilinx.com. at www.rscahners.ims.ca/ednmag.

-by Brian Dipert