Self-modifying code extends addressing mode

Paul Sofianos, Motorola Inc, Tempe, AZ

As just about any assembly-language programmer knows, self-modifying code (SMC) is usually undesirable, unintentional, and destructive. However, the SMC routine in Listing 1 is extremely useful to extend the indexed, 16-bit offset addressing mode of the venerable HC05 µC from 8 bits, or 256 locations, to the full 13-bit (8-kbyte) memory address space that the µC’s architecture supports. This routine is very useful for error tables, text messages tables, or any array manipulation for a large number of elements.

Indexed addressing with offset is useful for selecting an element of byte length, L, in an N-element table. In general, you calculate the effective addresses of this element as follows:

EA=TA+L3N+EO,

where EA=effective address of the memory location; TA=the absolute address of the start of the element table; L=number of bytes associated with each table element; N=the desired element number, beginning with zero; and EO=element offset, which includes all integer values from 0 to L–1.

The HC05 calculates the quantity L3N+EO and places the result in the index register. The µC then adds this dynamic value to the static quantity, TA, to arrive at the effective address. Unfortunately, the index register of the HC05 is only 8 bits long, limiting L3N+EO to values of 0 to 255, which is inadequate for large tables.

The SMC routine in Listing 1 easily overcomes this limitation. Simply put, the routine copies a dummy static-command set that employs extended addressing from ROM to RAM. The code calculates an effective address for EO=0 and stores the result as an absolute address, such as TA, for this RAM command. The code then executes this RAM command, fetching a single byte from ROM at an absolute, extended address and saving the byte in RAM by using indexed, 8-bit offset addressing. The routine fetches successive memory locations from the data table and places the contents in the target table in RAM. This process continues until the transfer of all L bytes of the desired element is complete. (DI #2280)

VHDL procedure dynamically opens a file

Jacques Behar, Rockwell Semiconductor Systems, San Diego, CA

A simple VHDL-87 procedure opens a file whose name a command file or user conveys in runtime. You can apply this technique to the reading or writing of data, control, and status files. This procedure is useful for replacing the input stimuli file of a testbench withoutrecompiling the code (with a different stimuli file name) or rename the stimuli file name. In addition, the procedure can write the simulation results to a file whose name consists of the input file name and any preferred extension.

The example in Listing 1 shows the skeleton of a program that reads and sums a file of integers. In this example, the program first reads the input data file name from the command file "name.cmd" in the first four lines after "begin." Alternatively, the user can interactively enter the data file name. A VHDL procedure embedded in a concurrent VHDL process achieves the dynamic file access. The main process uses the READ_NEW_INT signal to activate the concurrent READ_FILE process in this example (Listing 2). Upon activation, the READ_FILE process invokes the READ_FILE_ PROCEDURE. The FILENAME signal conveys the name of the read file. Note that the length of the file name is also necessary, and the FILENAME_LEN signal conveys this length to the READ_FILE procedure.

The MAIN process has sole control over each access to the input file, which is obvious in this simple example that reads a new integer each time the MAIN process toggles the READ_NEW_INT signal. In some complex cases, the MAIN process could conditionally open a file after part of the simulation is complete. At the end of the file, the procedure exits automatically, and the file closes. (DI #2281)

Configure buck converter for boost operation

Mehrzad Koohian, Semtech Corp, Newbury Park, CA

Buck converters are inherently different from boost converters, because buck converters typically use the high side of the output as the power switch’s reference. However, a buck converter with a floating output drive section is configurable as a boost controller (Figure 1). This circuit configures the SC1101 buck controller for a 5 to ±12V boost with ±500 mA of output current. The BST pin, which normally connects to a high-side drive supply in a buck converter, connects to V_CC to drive the ground-referenced MOSFET. By tying PGND to circuit ground, the SC1101 becomes a boost controller, yielding 12V from 5V. An output charge-pump voltage inverter provides –12V at 0.5A as well.

The sense resistor, R₁, serves two purposes. First, it assures proper start at power-up with full load by limiting the duty cycle. With the output capacitors not charged, a full-load condition demands high peak inductor currents. If the duty cycle exceeds a maximum limit, the inductor does not have a chance to discharge and will saturate. By limiting the peak currents and thus the duty cycle, the output capacitors can charge in several cycles upon start-up, thus preventing inductor saturation. R₁ also limits switch current during an overload or short circuit. In this application, a value of 0.012V provides for peak-current limiting and allows the circuit to deliver the required output current of ±500 mA.

A fast silicon rectifier, D₃, rather than a Schottky diode, rectifies the 12V output. Use of the silicon rectifier balances the voltage drops in the –12V rectifier circuit, which is two Schottky-diode drops, with the 12V rectifier drop. Because the application is power-limited, the circuit can trade off current that the –12V supply draws for current on the 12V output. If the –12V output is unused, the 12V output can deliver 1A, and you can eliminate D₁, D₂, C₁, and C₂. To improve efficiency under this condition, you can also use a Schottky diode for D₃. The controller provides separate grounds for power drive reference (PGND) and analog-circuitry common (GND). These two grounds must connect at the controller.

With dual outputs, the circuit’s measured efficiency is 91% with V_IN=5V and 93% with V_IN=5.5V. In Figure 1’s circuit, L₁ consists of a #T37-52 core (Micrometals Inc, www.micrometals.com) with 34 turns of 26-gauge wire. For applications that exceed ambient temperatures of 50°C, you can use a slightly larger core, such as a #T38-52, or a Kool MU core material available from Magnetics Inc (www.mag-inc.com). (DI #2279)

Circuit eases three-phase monitoring

Henno Normet, Tavares, FL

Measuring line-to-line voltages in a delta-connected three-phase system can present special problems. Because all three lines may be floating several hundred volts above ground, you can not use nonisolated, grounded oscilloscopes or other single-ended instruments. Special isolation amplifiers are available for oscilloscopes, but they can cost several thousand dollars. You still need to make three measurements even with proper instrumentation. The circuit in Figure 1 reduces the magnitude of the line-to-line voltages and combines them into one ground-referenced signal (Figure 2) that you can safely monitor with a grounded oscilloscope.

Phase C serves as a floating common (ground) for the circuit. Unity-gain buffer amplifiers IC₁ and IC₂ prevent loading of the 30-to-1 voltage dividers connected from A to C and from B to C. Op-amp IC₃ is a differential-input instrumentation amplifier that provides a signal proportional to the voltage between A and B. Unity-gain amplifier IC₄ inverts the B-C signal such that the half-wave-rectified signals can combine with the proper 120° phasing. The forward voltage drops across D₁ to D₃ cause a small error. You can minimize this error by using germanium diodes (1N34s), which have lower voltage drops than their silicon counterparts, and by keeping the signal levels as high as possible.

All the circuitry floats at power-line potential; thus, it is dangerous to monitor the rectifier outputs. To obtain a safe output, you should use an ISO122P isolation amplifier. The ISO122P is a unity-gain amplifier with an output that is fully isolated from its input. You need two line-isolated ±15V supplies to power the ISO122P and the op amps. The circuit has additional applications, the details of which are beyond the scope of this Design Idea. For example, in some cases, it is important that the three phase voltages are equal (balanced); their absolute values may be of less importance. It is much easier to detect an imbalance looking at a single waveform than it is looking at three waveforms. For continuous unattended monitoring, the design needs only one undervoltage/overvoltage detector, rather than one detector for each of the three phases. (DI #2283).

PLL forms simple MSK demodulator

Tom Napier, North Wales, PA

In minimum-shift-keying (MSK) signaling, two frequencies that differ by the bit rate represent a one bit and a zero bit. Normally, the frequency shift occurs at the peak of a cycle, so that neither the amplitude nor the slope of the waveform shows a discontinuity. We needed to transmit 300-baud ASCII text using ultrasonic transducers. These devices have a very narrow bandwidth around their 25-kHz resonant frequency, making MSK the obvious choice for modulation. A zero bit becomes 84 cycles of 25.2 kHz, and a one bit is 83 cycles of 24.9 kHz. It is easy to generate this signal with a PIC µC and an 8-bit DAC. However, a traditional MSK demodulator circuit uses a center-frequency VCO and several mixers and filters. This design needs something simpler: to wit, the circuit in Figure 1.

Because the transmitter sends 25.2 kHz between characters, the design phase-locks a 74HCT4046 PLL chip to this frequency. The chip has three phase detectors, each with different characteristics. By choosing the correct two, you can demodulate the MSK input without losing phase lock on the zero-bit carrier. Phase Detector 3 on the PLL chip has a 360° linear range. That is, its mean output varies from 0 to 5V and then switches back to 0V as the phase passes through 360°. Adjust the frequency of the PLL chip so that it locks to 25.2 kHz with a 180° phase error and an output of 2.5V. If the oscillator frequency remains fixed, then you can recognize a one bit by its phase error, which swings from 0 to 360° during the bit.

Because the initial lock is at the 180° point, a one bit results in a phase error that goes from 180° down to 0°. It then jumps to 360° and continues back down to 180°. The net result is a ramp that goes down to 0V, a jump to 5V, and then another down-going ramp. The mean voltage is 2.5V. Because the loop bandwidth is approximately 15 Hz, the instantaneous effect on the VCO is small, and the net frequency change is zero. Rather than detect the ramp-jump-ramp waveform, use Phase Detector 1 as the data output. Because this block is a simple exclusive-OR gate, each one bit appears as a spike going from 5 to 0V and back. A comparator can change it into a return-to-zero version of the input signal. Alternatively, the output can go to a retriggerable monostable with a 3.5-msec period to generate a good approximation of a nonreturn-to-zero output. Figure 2 shows the circuit waveforms that occur for the letter "g." (DI #2284).

µC makes inexpensive sine-wave generator

Jorge Luis B Romeu, IdeaWorks LTD, Syracuse, NY

You can use A/D converters or external, controllable oscillators to generate sine waves from low-power, low-cost µCs. However, these methods add cost, reduce reliability, increase circuit and software complexity, increase power consumption, and increase overall size. Alternatively, and with just a few lines of code, most µCs can easily generate multiple discrete sine waves. The example in Figure 1 uses a 68HC705J1A to generate sine waves of 9 to 20 kHz. The circuit uses the µP’s square-wave output and switches between multiple RC filters of varying cutoff frequencies to achieve outputs with reasonable spectral purity.

The necessary code consists of a simple subroutine that can adapt to different needs, such as tone duration and multiple (sequential) tone output (Listing 1). Moreover, the generated frequency is based on a variable, "frec," that a previous routine can pass to this subroutine. The duration time is based on a timer, which eliminates calculations of tone duration based on the cycle period. The code in Listing 1 is for illustrative purposes, but you can use it as-is with proper headers.

The basic circuit in Figure 1 uses only four output pins of the µC; three pins are for filter returns, and the fourth is the µP output. The filter constants are such that the highest cutoff frequency corresponds to the highest generated frequency. The subsequent cascaded filters cut off at lower frequencies, and the circuit can switch these filters in or out depending on the desired output (Table 1). The µC’s speed, code efficiency, the number of discrete frequencies to be generated, and the spacing between those frequencies all determine the maximum frequency of operation. The number of loops for one-half cycle of output frequency (50% duty cycle) equals the number of cycles per loopXtime/cycle. With a 3.58-MHz crystal, the time per software cycle is 558 nsec. (The 705J1A µC uses one-half of the oscillation frequency for its internal operating frequency.) Table 1 shows some example frequencies and the corresponding number of loops.

The RC filters have a cutoff frequency, or –3-dB point, at the generated frequency for maximum linearity and minimum distortion. You should note that the output is approximately the same level across all frequencies because the resistors are always in series when driving a high-impedance load. However, because of leakage when a capacitor is active, or grounded, the lowest frequency has a lower output than the highest frequency. You should optimize the R and C values in Figure 1 for your application, desired output frequencies, and impedance. You can switch the filters on and off sequentially, independently, or in combinations to suit different needs. (DI #2278)

74ACT74 makes low-skew clock divider

Tom Napier, Consultant, North Wales, PA

Serial-data systems often generate an internal clock at twice the data rate for mid-bit sampling or for generating bi-phase codes. External equipment and some internal processes require a clock that runs at the data rate. Simply dividing the twice-rate clock with a flip-flop generates a data-rate clock that is skewed by one logic delay with respect to the input. This delay can be a significant fraction of the bit period. You can use specialized PLL-based low-skew divider chips to deal with this problem, but these chips have a limited frequency range and are not designed to follow rapid changes in the data rate.

The circuit in Figure 1 uses a dual flip-flop, the 74ACT74, to generate both clock rates as well as both clock polarities with negligible skew. One half of the chip, IC_1A, acts as a normal divide-by-two circuit. The other half, IC_1B, tracks the input clock because the input’s leading edge triggers IC_1B high and the input’s trailing edge resets IC_1B. The divider transitions are synchronous within a few hundred picoseconds with the positive transitions of the twice-rate clock that the chip’s other half generates. This circuit works with inputs from a few hertz to more than 100 MHz.

Without R₁, the input removes the reset from the twice-rate flip-flop at the same moment as the input clocks this flip-flop on. Theoretically, this setup is allowable because the 74ACT74’s reset-recovery time is specified as 0 nsec. In practice, a resistor in the 100 to 500V region, in conjunction with the chip’s input capacitance, delays the clock inputs slightly and adds a useful safety margin. (DI #2282)