Design Ideas

RISC µP implements fast FIR filter

Sorin Zarnescu, NEC Electronics, Santa Clara, CA

When it comes to implementing a fast FIR filter, current RISC µPs can compete with DSP µPs. The FIR algorithm continuously implements the following equation:

N=n–1

Out=Sum[in(t[-]n)coeff(n)]

N=0,

where N is the number of taps, or the number of multiply-accumulate (MAC) instructions of the filter.

Using a delay line to implement this equation is common and involves the ability to manage a circular buffer. Specialized DSP µPs have can manage this task in hardware, and general-purpose µPs have to implement the buffer management in software. As you might expect, the software implementation is significantly slower than the hardware one. However, modern RISC µPs operating at high speeds and with features lacking in previous generations of general-purpose µPs can compete in price and performance at executing these types of algorithms.

For example, consider the following algorithm, which you can implement using the V832 RISC processor (NEC Electronics, www.el.nec.com), which runs at 144 MHz. This µP features large internal memories, the ability to execute instructions from internal memory in one clock cycle, and the ability to execute one MACinstruction in one clock cycle. The algorithm is not new, but it takes advantage of these features.

The algorithm runs linearly with no loops and implements the circular buffer with the addition of load/store instructions. Because the V832 is a RISC processor, arithmetic operations can take place only between registers. When a new sample is available, data loads from memory into the registers; the algorithm operates on the data and then stores it back in memory. The trick is to store the data back into the memory but shifted by one position. For the simple case of a four-tap filter, the algorithm looks like Figure 1.

For each tap, the processor needs to execute only ld.h (load the sample into the register), maci (multiply-accumulate immediate, in which the immediate value is the coefficient), and st.h (store the register back into the memory according to Figure 1).

Listing 1 comprises sample code for a four-tap FIR filter. The instruction arrangement minimizes the dependencies inherent in a pipeline-based µP. The next time the program executes, all of the samples are in the right position, assuming that the ADC interrupt routine writes the new sample into M1 before calling the filter routine. Regardless of the number of taps, the program takes three clock cycles per tap, which in the case of the V832 translates into 21 nsec/tap and occupies 3N memory locations. (DI #2313).

Simple algorithm transforms filter coefficients

Frank Vitaljic, Bellingham, WA

To synthesize infinite-impulse-response (IIR)-filter functions, expressed as H(z), you commonly use analog prototype-filter functions, expressed as H(s), using the bilinear-z transform. This operation entails some algebraic complexity in calculating the filter coefficients. The simple algorithm shown here transforms the prototype-filter coefficients (W₀, W₁, W₂) to the IIR digital-filter coefficients (U₀, U₁, U₂). These coefficients transform from the s (analog) domain to the z (digital) domain as:

The filter conventions are:

where the numerator and denominator polynomials undergo independent transformation. The matrix equations are

where

and, for first-order filters,

These equations assume that the prototype filter is normalized with respect to the sampling frequency, f_S. For example, design a second-order Butterworth unity-gain, lowpass IIR filter with cutoff frequency, f_c,=100 Hz, and sampling rate, f_S=1000 Hz. First, you use C_W to frequency-scale the Butterworth prototype (in normalized form, C_W=1). The expression for C_W is

The prototype filter is thus

Now, calculate the IIR coefficients using the transform in equations 1 and 2:

Figure 1 gives the filter’s flow diagram. (DI #2287).

Door/window sensor resists tampering

Paul Nocella, Q Research, Brookline, NH

The simple, inexpensive circuit in Figure 1 detects a failure (or deliberate tampering) on lines connected to normally closed switch sensors. For example, common door interlocks and door/window sensors consist of normally open or normally closed magnetic reed switches. Depending on the monitoring configuration, an open or short on a line may go undetected, thus preventing alarm activation. Embedding a resistor in a normally closed sensor and using bipolar dc power supplies produces the balanced configuration in Figure 1. A short or open on a line (or sensor activation) produces a net positive or negative voltage at the input of the Q₁-Q₂ pair.

A positive-voltage imbalance turns Q₁ on; a negative-voltage imbalance turns Q₂ on. The back-to-back clamping action of the base-emitter junctions of Q₁ and Q₂ protects the transistors from excessive reverse VBE voltages. The clamping prevents intrinsic base-emitter zener breakdown. R₃ limits the input current to Q₁ and Q₂ in the event of a line short. The collectors of Q₁ and Q₂ form a wired-OR configuration that turns Q₃ on by pulling its base toward ground. Q₃ provides gate current to trigger the alarm, SCR Q₄, which can handle several hundred milliamperes. Q₄ can drive a variety of alarm indicators, including LEDs, piezoelectric buzzers, or relays that control high-power alarms.

It’s easy to add monitoring locations, simply by adding sensors in pairs and replicating the Q₁-Q₂ circuit configuration, including the wired-OR connection to R₅. With power-supply voltages of ±5V, worst-case resistor tolerances of ±5% and a 2.5% supply imbalance do not cause Q₁ or Q₂ to turn on. The ±5V supplies should rise approximately simultaneously; otherwise, a net voltage imbalance would appear at the input of Q₁ and Q₂, resulting in alarm activation. Momentarily opening S₃ resets Q₄ by interrupting its anode current. C₂ provides a small time delay to allow the voltage at the input of Q₁ and Q₂ to stabilize before enabling Q₃. C₁, C₃, and C₄ prevent stray ac pickup or transients from triggering Q₄. (DI #2286).

Use a trick to count scope events

Allen Montijo, Hewlett-Packard, Colorado Springs, CO

One advantage digital storage oscilloscopes (DSOs) have over analog scopes is trace persistence. You can easily see infrequent waveform features using a scope in infinite-persistence mode. However, the frequency of these features relative to that of a "normal" signal can sometimes be less than obvious. You may wonder, does that glitch appear 10% or only 1% of the time? And how often does that short clock cycle occur? When you take trace noise into account, even a color-graded display does not directly or accurately give the information. A histogram is the most accurate way to give the information, but it requires time and expertise. The following hint provides a quick way to determine, using a DSO, how often each of two waveforms occurs.

First, use a standard nonaveraging mode to find the voltages of the two states at a fixed point in time (V₁ and V₂). Now, turn averaging on using a large number of averages. After the trace settles, measure the average level(V_A). The percentage of time the signal at V₂ is:

The accuracy of your answer depends on the accuracy of your V₁, V₂, and V_A measurements. To increase the accuracy of V_A, simply increase the number of averages on the scope. If you can use your DSO’s advanced triggering capabilities to trigger on only one waveform, then you can use the DSO’s averaging mode to make more accurate measurements of V₁, V₂, or both. (DI #2298).

A primer on binary-arithmetic rounding

Tom Balph, Motorola SPS, Tempe, AZ

As digital communications and data compression/decompression proliferate, signal-processing functions grow in importance. Whether you’re dealing with hard-wired logic or programmable engines, an understanding of binary-arithmetic rounding is important in getting correct and consistent results. Before we discuss rounding, consider a binary number (Figure 1).

At first glance, rounding seems a simple matter. However, several variations on rounding exist. Depending on the application, you may use one of the following techniques:

• Truncation (round to minus infinity)—This form of rounding ignores any information in the fractional value to the right of the binary point. You discard these bits, leaving the integer value to the left of the binary point unaffected. Truncation is also called round to minus infinity because it has the effect of rounding to the more negative number. Truncation is in wide use because it is simple to implement: Just ignore the unused bits.
• Round to plus infinity—This variation is essentially the inverse of truncation. If the fractional value to the right of the binary point is not exactly zero, then you round up (make more positive) the integer value. The implementation is more complex than truncation, because you must test all the fractional bits for the existence of a one and then increment the integer value if you find a one.
• Round to zero—Round to zero applies to 2’s complement numbers. (For the case of positive numbers only, round to zero reduces to truncation.) For negative numbers, this rounding technique depends on the fractional value—the existence of any nonzero LSBs causes a round up to a less negative number. The positive-number case is simply truncation. The implementation must consider both the fractional-number value and the sign bit. You increment the integer value only when the sign bit equals one (negative number) and the fractional value is not zero.
• Up-magnitude (round to infinity)—Up-magnitude is the inverse of round to zero and applies to 2’s complement numbers. If the number is positive, round up for any fractional number not equal to zero. If the number is negative, round down (truncate) for any fractional number not equal to zero. This algorithm is perhaps most useful for maintaining the largest possible magnitude for digital-to-analog conversion. The technique finds use in recent standards, such as ISO/IEC 11172-3 MPEG audio. Implementation again considers the sign and fractional values: Increment the integer only when the sign bit equals zero (positive number) and the fractional value is not zero.
• Simple round (2’s complement round)—Simple round applies to both magnitude-only and 2’s-complement numbers. You round up the integer value for all fractional values greater than or equal to half the full-scale value of the fractional number. Half the full-scale value is a one and all zeros at the right of the binary point. For fractional values lower than half full-scale, the integer number remains unchanged (truncation). Implementation is relatively simple in that you can add a one to the number at the bit position directly to the right of the binary point. This action increments the integer for any fractional value equal to or greater than half the fractional full-scale value.
• Convergent round—Convergent round is similar to simple round. The difference has to do with the half-full-scale value of the fractional number. A fractional number greater than half full-scale always causes rounding up of the integer number, a fractional number less than half full-scale causes the integer to remain unchanged, and a fractional number equal to half full-scale causes the integer to round up to the nearest even value. Convergent round is most useful for iterative processes in which cumulative addition causes errors to occur more readily. Implementation requires testing the fractional value, as well as the LSB of the integer number. The integer number increments if the fractional value is greater than half full-scale or if the fractional value equals half full-scale and the integer LSB is one (producing an odd number).

Listing 1 illustrates the rounding methods using Verilog HDL. A 12-bit number, "x," with the binary point located to the left of Bit 3 serves as the input (yielding an 8-bit integer and a 4-bit fraction). Each of the rounded results are 8-bit integer numbers. Part A of Listing 1 is the module listing, which defines and exercises the rounding outputs and displays the results. Part B gives the displayed simulation results, which you can use to observe the rounding differences. Be aware that, although this HDL routine is fully synthesizable, the resulting logic may not deliver the best performance or be the minimum configuration.

When you implement rounding, performance can suffer if an additional add occurs, because of the rounding algorithm. At times, however, the logic producing the original number can hide the additional add. As an example, if you use simple round (2’s complement round) with a multiplier to round the results, a constant one can appear in the partial-product array (at the proper location), and summing the one along with all the partial products produces no loss in performance. Here, the increment of the integer product is buried in the multiplier-adder array. (DI #2285).

Light powers isolation amplifier

Stephen Woodward, University of North Carolina, Chapel Hill, NC

Self-powered isolation amplifiers, which need no external isolated power supply, provide versatile and convenient interfaces in many applications that require galvanic isolation of the signal source. Examples of such applications include circuits that serve in industrial or medical environments, in which isolation is necessary for noise reduction or safety. You can use a variety of isolated signal-coupling techniques for the signal paths of these amplifiers. Transformers, differential-capacitor, and opto- isolator schemes are all popular choices. For the internal isolated power supply, transformer coupling is virtually universal, despite the problems inherent in inductively coupled circuits. These problems include relatively high interwinding stray capacitance and a tendency to couple switching noise into the signal. In contrast, the self-powered amplifier in Figure 1 is different in that it incorporates optoisolators to effect communication of both signal and power around the isolation barrier.

As in many isolation-amplifier designs, the signal processing in Figure 1’s circuit uses PWM. The isolated-modulator front-end circuitry derives from an earlier ADC design and works as follows. IC₁ compares the ±1V filtered input signal with the voltage on C₁. The R₄C₄ time constant smoothes IC₁’s output, and IC₂ compares the output with IC₃’s approximately 1-kHz triangle waveform. R₁, R₂, and C₁ scale and average the resulting variable-duty-factor square wave and feed the signal back to IC₁. This feedback loop continuously adjusts IC₂’s duty factor to maintain equal voltages on C₁ and C₂. In doing so, the feedback forces IC₂’s output square wave to track the unique T₊/(T₊+T_–) duty factor that maintains balance at IC₁’s inputs.

C₅ differentiates the IC₂ square wave to provide bipolar drive pulses to the antiparallel LEDs in the high-speed, low-current optoisolator OI₂. In turn, OI₂ produces ground-referred pulses. The rather unusual RS flip-flop formed by cross-connected switches S₁ and S₂ converts these pulses back to a logic-level square wave having the same duty factor as IC₂’s output. Demodulation and filtering of the square wave to accurately reproduce the original analog signal occurs through the action of the single-pole, double-throw switch, S₃, which chops the 2.500V V₂ reference voltage according to the T₊/(T₊+T_–) square-wave duty factor. The lowpass, gain-of-two filter, IC₅, then extracts the dc component of S₃’s 0 to 2.5V waveform and scales and offsets it to produce a low-ripple, ±2.5V signal, according to the formula

Power for the isolated-modulator side of the amplifier comes from OI1, an International Rectifier (El Segundo, CA) PVI5100 photovoltaic opto IC. Marketed as an isolated MOSFET-gate driver, the PVI5100 can source approximately 20 µA of current at 4V (80 µW), just enough to keep the anorexic LT1443 alive and functional. IC₄ shunt-regulates OI1’s output to provide a stable 4V ratioed against the MAX924’s 1.2V±1% internal reference. Overall frequency response is dc to 10 kHz; input impedance is approximately 1 T with less than 1-pA bias. The circuit can thus provide good overall accuracy with high-impedance input sources. You can trim gain and offset errors to zero; the excellent drift specs of the LT1443 maintain the trim over temperature. (DI #2304).

Low-cost feedback circuit boosts efficiency

John Guy, Maxim Integrated Products, Sunnyvale, CA

To implement a step-up converter with a current output, designers often simply connect the load in place of the top resistor in a resistive-divider feedback network. The bottom resistor then serves as a current-sense resistor. Though simple, this approach is inefficient. Low efficiency results from the relatively high sense voltages—usually, 1.25V but as high as 2.5V for some ICs. A switch-mode dc/dc converter configured as a 20-mA current source minimizes the efficiency loss by lowering the sense voltage to 200 mV (Figure 1). Advantages of this circuit include the factor-of-six gain in efficiency; minimal board area; and readily available, low-cost components. Applications include battery charging, LED drive, and general-purpose current sources.

Resistors R₁ and R₂ form a voltage divider that derives 200 mV from the IC’s reference output. This sense voltage connects to one emitter of the current mirror comprising Q₁ and Q₂. Both collectors connect to the output voltage via 200-k resistors. The collector of Q₂ also connects to the IC’s feedback pin, and Q₂’s emitter connects to the low-side current-sense resistor, R₅. The feedback network appears to the IC’s control loop as a common-base amplifier. Selecting a 2N3904 for Q₂ yields sufficient emitter-to-collector gain for the purpose: approximately 80V/V. Moreover, the network’s large bandwidth (characteristic of common-base configurations) prevents instability in the IC’s control loop. (DI #2307).