Design Ideas

Simple circuit provides efficient PWM

Kenneth Levine, Eldec, Lynwood, WA

You often need to control the duty cycle of a square wave. The circuit in Figure 1 works from a single 5V supply at a frequency of 100 kHz. With minor component changes, you can configure it for a range of frequencies. The circuit consists of a ramp (sawtooth) oscillator and a comparator. The circuit compares the ramp to an externally applied voltage, V_CNTRL. When V_CNTRL is greater than the ramp voltage, the PWM output is 5V. The sawtooth oscillator consists of a current source (R₁, R₂, R₃, and Q₁), a timing capacitor (C₁), and the oscillator-control circuitry (R₄, R₅, R₆, and IC_1A). The oscillator-control circuitry sets the upper and lower voltages of the timing capacitor at 3 and 1V.

R₁ and R₂ set the voltage at Q₁'s base to 1V. R₃ and the V_BE drop (0.7V) are in parallel with R₁, so the voltage across R₃ is 0.3V for a current of 200 mA. Because the emitter current greatly exceeds the base current, the collector current is nearly 200 mA. A capacitor receiving its charge from a current source charges linearly. The current in C₁ is 200 mA, and the change in voltage is 2V (1 to 3V). From I=CdV/dt, dt=10 msec, and the frequency is 100 kHz. The oscillator-control circuitry uses a comparator with hysteresis to compare the capacitor (ramp) voltage with the charge limits. An externally applied power-on-clear (POC) signal ensures reliable start-up. POC must connect to an open-collector device that pulls to ground at power-on and produces no voltages when inactive.

After removal of POC, IC_1A's Pin 5 is at ground, IC_1A's Pin 12 is at open-collector status, and IC_1A's Pin 4 is at 3V (the voltage across R₅). C₁ now starts charging. When the voltage on C₁ exceeds 3V, IC_1A's Pin 12 switches to nearly ground, IC_1A's Pin 4 drops to 1V (the voltage across the parallel combination of R₅ and R₆), and the charge on C₁ rapidly bleeds off through D₁. The discharge time is short enough to have a negligible effect on the oscillation frequency. When the voltage on C₁ drops below 1V, IC_1A's Pin 12 switches to open-collector status, D₁ stops conducting, and C₁ begins to charge again. The entire cycle repeats, creating sawtooth oscillation.The circuit creates PWM by comparing the voltage on C₁ with V_CNTRL. As long as V_CNTRL is greater than the voltage on C₁, the PWM output stays at 5V. You should limit V_CNTRL to a bit more than 1V and a bit less than 3V to prevent comparator oscillation. If the source of V_CNTRL can tolerate it, you can add hysteresis. The relationship of PWM to V_CNTRL is linear: PWM width=50(V_CNTRL21)%, valid for 1V< V_CNTRL<3V. To increase the operating frequency, you can replace the LM319 with a faster comparator. (DI #2309).

Visual Basic models MDAC offset

Olga Belousava, Los Alamos, NM, and Alex Belousov, New York, NY

It's hard to imagine that, for such an old-hat item as a standard R-2R multiplying DAC (MDAC), there still exists some "dark area" in modeling and calculating its dc offset, V_OFF, and related output resistance, R_O. You can obtain some information from References 1and 2 and other references regarding the code dependency of R_O and V_O, but the simplified formulas given therein are insufficient for thorough engineering analysis/design and computer modeling/simulation. Moreover, these formulas apply mainly to the case in which the reference pin (Figure 1) is open, whereas most MDAC applications connect the reference pin to a low-impedance source. Also, the source resistance, R_IN, has an impact on V_OFF and R_O. This Design Idea introduces an equivalent circuit for the MDAC and discusses mathematical models. A software program, "DAC Designer AO," simplifies the offset calculations. You can download the Visual Basic files by clicking here.

The models are based on the idealized R-2R resistive ladder in Figure 1 with zero on-resistance and infinite off-resistance in the switches and without current leakage or parasitic voltages. Figure 2 gives an equivalent reciprocal- network for the ladder, in which G₁₁ is the input conductance with the output terminals shorted, G₁₂ is the transfer conductance, and G₂₂ is the output conductance with the input terminals shorted. The applicable math formulas are as follows:

It's obvious that G₁₁ has a constant value, the reciprocal of the base resistance, R. G₁₂ is a linear function of the input code and base resistance R. The expression for G₂₂, however, reveals complex, nonlinear behavior as a function of the digital input code. A Thevenin transform in Figure 2's circuit produces the simplified equivalent circuit in Figure 3. The output resistance, R_O, in the most common case, when the MDAC connects to a low-resistance source, is the reciprocal of G₂₂. The offset voltage is thus

Table 1 gives the maximum theoretical values for V_OFF in 8- to 12-bit MDACs. You can easily obtain the exact values for V_OFF and R_O for any arbitrarily chosen input code by using the cited software program. The program also allows you to compute the statistics (maximum V_OFF , its mean, and standard deviation) for any predefined range of input codes. You can use the suggested equivalent circuit and mathematical models with any computer simulation packages in dc-analysis mode. (DI #2305).

References

1. Sheingold, Daniel H, Editor, Analog-Digital Conversion Databook, Prentice-Hall, 1986.
2. Data Converter Reference Manual, Volume 1, pg 2-540 to 2-541, Analog Devices, 1992.

Charge-pump circuit divides by two

Budge Ing, Maxim Integrated Products, Sunnyvale, CA

Small size and efficiency approaching 100% make switched-capacitor charge pumps popular for voltage doubling and inverting in miniature dc-dc applications. Few are aware, however, that most charge pumps can halve as well as double or invert an input voltage. The increasing adoption of low-voltage logic makes this ÷2 capability useful for generating low-voltage supplies in portable equipment. You can use it, for example, to convert a 3.6V RF-supply voltage to 1.8V for powering low-voltage logic (Figure 1). Simply reversing the input and output of a voltage doubler makes it a voltage divider. Implementing this scheme with MAX660 or MAX1683 voltage-doubler charge pumps requires only three external capacitors (Figure 2). Both configurations in Figure 2 accept input voltages of 3.6 to 10V, but they present trade-offs in size and output-current capability.

For 3.6V inputs, the robust MAX660, which comes in an eight-pin DIP or SO package, delivers 150 mA with efficiency greater than 88% and an output-voltage drop of less than 300 mV. If you require a smaller package, the MAX1683 (available in a five-pin SOT-23) offers 50-mA capability with a 3.6V input and as much as 100 mA with inputs higher than 8V. Its efficiency is 97% at 5 mA and 86% at 50 mA. Each device has an internal clock. The MAX660 runs at a nominal 10 kHz (with the FC pin open), and the MAX1683 runs at a nominal 35 kHz. Each divider's output resistance depends on the internal clock frequency, the flying capacitor (C₁), the resistance of the internal switches, and the resistance of the output capacitor C₂. You can calculate the output resistance by:

where f_OSC is the oscillator frequency, R₁ to R₄ are the R_DS(ON) values for the four internal switches, and R_ESR is the equivalent series resistance for the output capacitor, C₂. The graphs in Figure 3 illustrate the performance of the charge pumps operating in voltage-divider mode. Figure 3a shows the output resistance versus input voltage for the MAX1683. Figure 3b shows the same parameters for the MAX660. Figure 4 shows efficiency versus input voltage for the MAX1683 (Figure 4a) and the MAX660 (Figure 4b). (DI #2301).

Pass transistor lowers dropout voltage

Matt Schindler, Maxim Integrated Products, Sunnyvale, CA

With linear regulators,you measure dropout voltage, V_IN–V_OUT, at the minimum input voltage for which the IC sustains regulation. Low dropout means longer battery life, because the load circuit continues to operate while the battery discharges to a lower terminal voltage. The external transistor helps to form a linear-regulator circuit whose dropout voltage at 100-mA load current is only 10 mV (Figure 1). (The linear-regulator IC by itself specs a 100-mV dropout at 100 mA.) The external transistor also boosts the maximum available load current to 1A.

Unorthodox connections enable the IC to drive Q₁. Connecting Pin 3 to the transistor's base allows base current to flow through the internal switching MOSFET, out of Pin 4, and through R₂ to ground. The MOSFET then regulates V_OUT by controlling Q₁'s base current. Because C₂ sets a dominant pole that stabilizes the loop, you should choose a ceramic type or other low-ESR capacitor. C₂ improves the phase margin by forming a pole-zero combination that increases the phase at crossover. Q₁ saturates when the battery voltage drops low enough for V_OUT to drop out of regulation, and R₂ limits the base current for that condition to approximately 10 mA. Q₁'s collector-emitter voltage at saturation, 10 mV with 1-mA base current and 100-mA collector current, sets the dropout voltage for these conditions.

The measured dropout voltage varies with load current (Figure 2). The circuit delivers as much as 1A at 3.3V. You can adjust the output from 5.5V down to 1.25V using the formula V_OUT= 1.25[1+(R₃/R₄)], with appropriate changes to the value of R₂, using the formula R₂=(V_IN(MIN)–0.7V)/10 mA. Small components allow the entire circuit to occupy less than 0.24 in.² of board area. (IC₁ comes in an SOT-23 package.) (DI #2323).

PIC µC implements CRC-16 algorithm

Lon Glastner, Solutions Cubed, Chilo, CA

Detecting errors in serial data can be paramount in completing an embedded-control design. Determining which algorithm to use for detecting serial-communications errors depends on several factors. Ideally, the method should require minimal hardware and little computational power from your processor and still provide high-level protection against undetected data errors. The cyclic redundancy check (CRC) combines all these factors under one umbrella. A multitude of CRC flavors exists, including the Dow CRC (8 bits), CRC-16, and CRC-CCITT (both 16 bits). The CRC-16 uses a 16-bit shift register and can detect the following error types:

• any cluster of errors within a 16-bit section of data,
• any odd number of errors within the data field,
• all double-bit errors in the data field, and
• most large clusters of errors.

You can characterize the CRC-16 as both a polynomial expression and as a hardware-based shift register (Figure 1). You can implement a CRC-16 in a midrange PIC µC with minimal coding and without additional hardware. Selecting a µC with an on-chip USART, such as the PIC16C63, eases serial communications. This implementation does not focus on the mathematical proof of a CRC-16's error-correcting effectiveness. The CRC algorithm is so effective it's an industry-accepted method for detecting data errors. The heart of a CRC-16 algorithm is a shift register. You generate the shift register by shifting each data bit through the algorithm. In this implementation, the data shifts the most significant bit first, one data byte at a time.

Two temporary registers buffer the data to prevent the shifting from corrupting the data. The shift register comprises two separate 8-bit registers, CRC16_HI and CRC16_LO. The most significant bit of CRC16_HI is the location of Stage 16 (Figure 1). From the figure and Table 1, you can see that the result of XORing the input data bit and the contents of Stage 16 of the shift register determines the effect that new data has on the shift register. If the result is a one, then you must complement the contents of stages 2 and 15 before rotating the new data into the shift register. If the result is a zero, then the new data can rotate immediately into the shift register. Some housekeeping tips can be helpful here. The data transmitter should generate its CRC-16 in the same manner as the data receiver. Also, it's advisable to clean the CRC-16 shift register before rotating the first data bit of the data string into it.

How does the CRC-16 identify data errors? The simplest method is to attach the shift register to the end of the data string. In this implementation, the CRC16_HI register should follow the last byte of data sent. The CRC16_LO register follows the CRC16_HI register. If the receiving system computes a CRC-16 value from all the data bytes and the attached shift register (CRC16_HI and CRC16_LO), then the resulting CRC-16 code is 0000h. Any nonzero result indicates an error in the data. In some systems, an error may occur that results in all zeros being sent as the data and attached CRC-16. This type of error poses as error-free data. In these systems, you can overcome the false indication by complementing the CRC-16 before attaching it to the data string. The CRC-16 shift register generated by attaching the complement is always 800Dh.

The code fragment in Listing 1 generates a CRC-16 shift register on a byte-by-byte basis. You could embed this code within serial-receive and serial-send routines to provide a powerful error-detection tool. You can easily generate the CRC-16 on the fly, thus minimizing the use of processor resources (DI #2321).

Monostable makes low-cost F/V converter

Mark Brinegar, Dart Controls Inc, Zionsville, IN

The circuit in Figure 1 is a low-cost frequency-to-voltage (F/V) converter. Using a monostable (one-shot) multivibrator, the circuit accepts an open-collector square wave that varies in frequency from 0 to 10 kHz. The one-shot produces a pulse of a fixed width each time the input signal triggers it. The result is a variable-frequency, variable-duty-cycle signal at the output of the one-shot. The time constant determined by R₂C₁, 100 µsec, determines the width of the pulses the one-shot produces. This time matches the period of the maximum input frequency (10 kHz). The duty cycle of the one-shot's output is thus 100% when the input is at its maximum frequency.

The variable-frequency, variable-duty-cycle output of the one-shot is the input for the lowpass filter comprising R₃ and C₃. The net result is, as the input frequency varies from 0 to 10 kHz, the dc output signal varies from 0V to V_CC. You can alter the circuit to accommodate different input frequencies by simply adjusting the R₂C₁ time constant to match the period of the desired maximum input frequency. (DI #2322).