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Sign-off power network and EMI-analysis tool decrease delay from voltage drop
By Michael Santarini -- EDN, 5/26/2005
Synopsys has combined static- and dynamic-timing-analysis technologies to create PrimeRail, a tool it bets will become the sign-off tool for gate-level power-network analysis and transistor-level EM (electromigration) analysis. Rajiv Maheshwary, senior director of sign-off and power products at Synopsys, says that, as voltage drop becomes more common in large designs, it is having a greater impact on overall performance of ASICs and SOCs (systems on chips).
“Voltage drop is an increasing part of overall delay,” says Maheshwary. “At 90 nm processes, 10% of overall delay is a result of voltage drop, and, at 65 nm, it can be as much as 15%. A few years ago when signal integrity started to impact overall timing, full-chip sign-off tools for signal integrity emerged. Now, customers need such a tool for voltage drop.”
Thus, far the traditional static- and dynamic-timing-analysis tools have been inadequate for full-chip sign-off, Maheshwary says. Traditional gate-level static-power- and EM-analysis products, including the company’s AstroRail, are not thorough enough for use in full-chip sign-off because they neglect dynamic effects, such as on-chip decoupling capacitance and package parasitics. Similarly, gate-level dynamic analysis tools cannot analyze transistors, especially analog and memory, commonly in SOCs. And, says Maheshwary, dynamic transistor-level tools, such Synopsys/Epic’s RailMill, are too slow and cannot do full-chip analysis.
To overcome the shortcomings of traditional tools and create a tool thorough enough for full-chip sign-off, Synopsys gives PrimeRail a hybrid static- and dynamic-timing-analysis engine. PrimeRail also includes a built in RLC (resistance, inductance, and current)-extraction engine from StarRCXT, a kernel PrimeTime static timer for peak power or “vector-free analysis,” HSpice technology for characterizing standard cell libraries, and NanoSim technology for modeling memories. For power-network sign-off analysis, users precharacterize standard cell libraries and memory blocks and then run either RC or RLC on-chip extraction and RLC extraction on the package, all with PrimeRail. Designers then use PrimeRail for vector-based or vector-free power-rail analysis. For vector-free mode, Synopsys uses a PrimeTime kernel that looks at peak power analysis based on the IC design’s switching activity, which PrimeRail then uses for dynamic rail analysis.
After dynamic analysis, PrimeRail generates voltage drop and EM maps. “Once you do the dynamic voltage-drop analysis, you pass instance-specific voltage-drop information onto PrimeTime SI [signal integrity], which then does concurrent analysis of timing, signal integrity, and voltage drop,” says Maheshwary. For one beta customer, PrimeRail within eight hours analyzed a 20 million-gate design with 400 memories and IP (intellectual property) in a 130-nm process, and, for another beta customer, the product in just more than five hours, analyzed an 8 million-gate design with 100 memories and IP.
PrimeRail does not yet share ECO (engineering-change-order) data with tools further up in the flow. The company is working on integrating the tool with Synopsys’ recently announced IC Compiler to ease the implementation of corrections. The company is also looking at integrating it with its JupiterXT floorplanner in the hope of helping users gauge the impact of voltage drop on overall timing early in the layout process. The tool will likely see its widest use as a sign-off tool for full-chip, mixed gate-and transistor-level design, but it also analyzes transistor-level voltage drop and EM tools in memory blocks. “A lot of IDMs [integrated-device manufacturers] have in-house memory compilers, and now they can use PrimeRail to ensure what comes out of the compiler is immune to EM effects,” says Maheshwary. For transistor-level blocks, users run extraction and use the NanoSim to create memory models. PrimeRail then runs in dynamic analysis with package parasitics. A beta customer in 9.5 hours ran EM analysis on a 4-Mbit SRAM with 12 million transistors in 90-nm silicon.
Maheshwary says that EM analysis hasn’t yet become a problem for standard cell design. “We are seeing EM issues in memory cells, but for standard cells it may take some time. A lot of the IDMs we work with have homegrown approaches that look at current densities and measure whether traces are thick enough,” he says. “We think that is going to have to change over time, and we are addressing it before it becomes a mainstream problem.” PrimeRail is in limited production, and the company expects to offer it for general availability in September. The price for the tool starts at $172,000 for one-year subscription.
Synopsys, www.synopsys.com.
