Post a Comment
News and New Products
Emulators speed event-based verification
By Michael Santarini, Senior Editor -- EDN, 6/6/2005
Tharas Systems has released two new emulator systems that use multiprocessor SOCs (systems on chips). The single-user Hammer-S Class emulator has a capacity of 16 million gates and targets hardware designers needing to speed event-based verification. The multiuser Hammer M-Class emulator has a 64 million-gate capacity and targets hardware engineers who want to verify their designs, and, through the new Virtual Connect add-on, software engineers, wishing to get a jump on software development. Richard Curtin, senior vice president of marketing and business development for Tharas, says that the two new systems improve on the company's previous offering the, Hammer 100 system, on just about all fronts.
Whereas the Hammer 100 used 128 processors, had a 32 million-gate capacity, and ran an 8 million-gate design with a testbench operating at 4.5 kHz, the new S-Class uses 1024 custom processors, has twice as many gates, and runs the same 8 million-gate design at 50 kHz. The M-Class has 4096 processors, a fourfold gate increase, and the ability to run the same 8 million-gate design at 200 kHz.
Curtin attributes the speed and capacity improvements to the company's placing 32 of its Hammer 100 custom processors on one SOC. This approach increases the capacity and exponentially speeds the emulators and allows Tharas to offer the systems in a form factor the size of a big toaster. Tharas also custom-designed the instruction set to handle Boolean operations for simulation. Custom instruction-set simulation speeds emulation. The company has also worked extensively on the compiler to help users quickly load their designs onto the emulator systems. Curtin claims a 50 million- to 60 million-gate compilation time. The emulators accept Verilog and VHDL design files, assertions in OVL (object-verification language), OVA (Open Vera assertion), and PSL (property-specification language) and testbenches in Verilog, VHDL, or C/C++.
Tharas also offers a software add-on that allows embedded-system engineers to get a jump on software development. The company's Virtual Connect add-on has three flavors of software models targeting popular market segments: the Virtual-PC platform for graphics applications, the Virtual-Net for networking applications, and Virtual-3G for wireless applications.
Curtin says that most users are designing ASICs with 5 million to 6 million gates. "A 16 million-gate system such as the S class should cover most design groups for the next couple of design projects," he says, arguing that manufacturers will realize the value of the emulator for its increased speed versus simulation over the life of the system. Prices for The Hammer S Class start at $200,000 for a 4 million-gate configuration, and prices for the M-Class start at $750,000 for a 32 million-gate configuration. Tharas also rents its emulators. Price of an S-Class rental in an 8 million-gate configuration starts at $21,000 per month. Price of an M-Class rental in a 32 million-gate configuration starts for $52,000 per month. Prices for the Virtual Connect add-on start at $75,000.
