Sequential channel selector simplifies software

Alex Knight, Cummins Engine Co, Columbus, IN -- EDN, 1/4/2001

An efficient but powerful circuit is useful for a variety of applications with limited I/O and for which you want to use one input to sequentially select a different output channel (Figure 1). When the software changes the state of only one input, the circuit sequentially selects one output channel at a time for test purposes. Because the test-application environment is potentially harsh, the circuit must have relatively high noise immunity and transient protection at the inputs. You must also be able to reset the circuit to resynchronize the hardware with a test program after any interruption in testing.

Although the resulting circuit may seem simple and standard, it is distinctly robust. The delayed reset signals at IC₂'s Pin 1 and IC₃'s Pin 2 return the counter and flip-flop ICs to their initial state so that OUT₁ is the first channel active at the first count. The power-on and switch-activated reset circuit includes R₁, D₃, and D₄ to protect against ESD that could arc over the switch contacts when someone first touches the switch. The IN signal input circuit has similar transient protection with R₂, D₁, and D₂. A simple RC oscillator generates the clock signal at IC₂'s Pin 9, and the second four-stage binary- ripple counter, IC₃, divides this clock by 16. The oscillator frequency is approximately 21 Hz, but you can change R₃ and C₁ to produce the desired frequency, which is approximately 1/R₃C₁. You can also use a potentiometer in place of R₃ to make the frequency adjustable. Keep in mind that the flip-flop clock-cycle period should be much less than the expected active and inactive periods of the IN signal but long enough to produce adequate debouncing of the input signal to maintain good noise immunity. The circuit serves a low-speed application, so the clock at IC₂'s Pin 9 is 1.3 Hz.

The circuit filters and buffers the IN signal before sending it to the flip-flop input at IC₂'s pin 4. The Schmitt inverter, IC₁ with its built-in hysteresis and the cascaded flip-flop circuit provide high immunity to noise, and the cascaded flip-flop ignores any glitches on the input signal that occur asynchronously to the flip-flop clock signal's positive-going transitions. The circuit uses the

output signal as the CLK_A clock input to the first four-stage binary ripple counter, IC₃. Negative-going transitions increment the counter as the timing diagram indicates at counts 1, 2, and 3 (Figure 2). The circuit uses the Q₂ output to select the active-high CS₁ chip-select input of IC₄'s one-of-eight decoder, which allows plenty of time for the ripple counter outputs to stabilize, even at high flip-flop clock speeds. These outputs do not simultaneously change states. With CS₁ high, the positive-going Q₃ output signal at the LE input of the decoder (IC₄, pin 4) latches the output channel that the state of the A₀-to-A₂ address inputs select. Latching the output channel ensures you that any subsequent noise-induced counter-output state changes will not affect the output-channel states. While CS₁ is low, the Y₀-to-Y₇ outputs from IC₄ are also low. This design maintains a similar off-time for all of the output channels, as reflected in the input signal, although the circuit delays any change of state for each of the outputs by approximately two cycles of the flip-flop clock period.

IC₅ can drive loads that sink as much as 350 mA at room temperature, such as relays, solenoids, dc motors, and lamps. This eight-channel source-driver IC is unnecessary if CMOS outputs suffice as the channel-select signals. The IC₅ source voltage can climb to 35V if you add a separate supply. IC₅ has internal diodes on all of the outputs to clamp inductive spikes.

The circuit includes a switch for generating a reset signal, which you can use in addition to or instead of an external reset signal. The input can also be an external analog signal or non-TTL, as long as you properly compensate for any dc offset necessary to work at the switching thresholds of the Schmitt inverter. You can cascade additional ripple-counter stages and add decoders and output drivers to select from more output channels.