News and New Products

Architecture targets USB applications

By Michael Santarini -- EDN, 7/6/2005

Structured-ASIC start-up ChipX, formerly Chip Express, is releasing a new structured-ASIC architecture with an initial device family focusing on applications using USB 2.0. Elie Massabki, vice of president of marketing at ChipX, says that the new CX6000 architecture offers users two, three, or four metal layers to design with in an architecture that comprises eight layers. Users can customize metal layers three through six, but layers one and two handle local interconnect, test lines, and a clock tree, and layers seven and eight hold the power grid.

ChipX implemented the devices in UMC’s (www.umc.com) 130-nm process have a maximum operating frequency of 250 MHz and a normal operating voltage of 1.2V. The CX6000 devices feature four low-jitter corner PLLs operating at 10 MHz to 1GHz and synthesizable DLLs running at 50 to 500 MHz for deskewing and frequency multiplication. The family features synchronous SRAM in 9-kbyte blocks, which designers can configure in the devices’ programmable metal layers as 1024×9, 512×18 and 256×36 bits. Each of those blocks is writable in 9-bit wide words and come in single-port, dual-port or FIFO versions; average single and dual ports run at 740 MHz at 1.2V. Memory blocks have a BIST (built-in-self-test) controller.

I/O structures include LVTTL (low-voltage transistor-to-transistor logic), low-voltage CMOS, 840-Mbps LVDS (low-voltage differential signaling), LVPECL (low-voltage positive-emitter-coupled logic), HSTL (high-speed transceiver logic), SSTL (stub-series-terminated logic) 18/2/3, DDR, PCI, PCIX, and XOSC. I/O voltage ranges from 1.5 to 3.3V, and individual drive strength ranges from 2 to 16 mA.

The first offering in CX6000 family is the CX6200, which targets applications using USB 2.0. “USB is a large market and an industry standard, and there is a great need in the market for USB in a structured ASIC,” Massabki says.

Wouter Suverkropp, strategic marketing director, says that, because USB requires a full subsystem including PHYs (physical layers), controller IP (intellectual property), and a processor, the devices have been difficult to implement on standard-cell SOCs (systems on chips) and have been virtually nonexistent on FPGAs. According to Massabki, 6 million USB devices are on the market this year and that number should increase by 2 million over the next two years.

The CX6200 includes a full subsystem for USB applications, including the USB 2.0 high-speed, USB OTG (On-the-Go) PHY and controller IP and a synthesizable 8051 processor to control the USB functions. The CX6200 devices have 140,000 to 1.8 million designable gates, 233 to 1037 Mbytes of memory, and 105 to 280 configurable I/Os, and 56-pin QFN to 456-ball BGA packages. Prices for the smallest CX6200 devices will start at $5 (100,000).

ChipX, www.chipx.com.