Testing serial gigahertz-speed buses

Engineers have for many years used wide parallel digital buses, such as PCI, SCSI, and parallel ATA, for interconnects in the computer and datacom industry. Over time, the clock speeds of these buses increased to several hundred megahertz. Although the pace may have slowed a little bit, the ever-increasing demand for more bandwidth naturally has led to ever-higher processor clock speeds. At clock rates of approximately 1 GHz, however, parallel buses have become roadblocks on the data highway. Currently, engineers could overcome these challenges, such as synchronizing parallel data lanes at rates greater than 1 GHz, only with massive, probably unjustified technical effort. This scenario is especially true if you consider that, all of a sudden, digital designers are in the realm of "digital microwave." Thus, they are often unprepared to cope with nasty effects, such as EMI and jitter (phase noise). Traditionally, such effects occur only in RF designs, and engineers could ignore them at lower data rates.

To overcome the physical limitations of the legacy buses and to cope with the new challenges, the trend is to migrate to serial, differential high-speed buses, such as PCI Express, SAS (serial-attached SCSI), or serial ATA (SATA). Figure 1 illustrates an example of computers using high-speed buses. Other examples include using PCI Express, RapidIO, and InfiniBand for chip-to-chip interconnects and on the bus and backplane level and using SATA on the system level.

In addition to overcoming the 1-GHz barrier, serial-bus implementations, such as PCI Express, offer significant advantages, including scalable performance, hot-plug and -swap capability, peer-to-peer communication without involving the processor, and low power consumption.

Clock speeds exceeding 1 GHz-for example, 1.5 GHz for SATA and 2.5 GHz for PCI Express-edge rates of less than 1 nsec, crosstalk, impedance mismatches, EMI, and jitter require careful modeling of the transmission channel. Coping with the effects of digital microwave requires innovative approaches. As an example, PCI Express uses spread-spectrum clocking to prevent EMI.

You need complementary, innovative test equipment to assist the design phase and for the verification and manufacturing test of the OSI (open-systems-interconnect) layers. The low-level PHY (physical layer) defines the physical characteristics of the signal-for example, the voltage levels and timing-to ensure the reliable transmission of the raw bits.

The following two examples provide state-of-the-art PHY testing with digital stimulus/response test equipment. On the stimulus side, this equipment typically comprises a pulse-pattern generator for generating flexible, high-quality test signals. A function generator might complement this digital workhorse by inserting jitter into the pulse generator's output signal. The response side typically uses oscilloscopes, sometimes with complementary logic analyzers. This article focuses on the requirements and capabilities of advanced pulse-pattern-generator and oscilloscope options using two examples: PCI Express receiver-design-validation test and SATA PHY-compliance test.

PCI Express, a third-generation I/O architecture, addresses the ever-increasing need for I/O bandwidth by providing a point-to-point, high-speed, low-pin-count option. As with each new architecture, you must resolve new interoperability and compliance design challenges. Various test-equipment vendors' tool sets help to quickly and efficiently resolve these new challenges.

You need to validate the proper operation of PCI Express transceivers. Validating the transmitter is straightforward. It simply connects to a logic analyzer or an oscilloscope, and you directly measure the waveform or eye pattern. The validation test of the receiver is more challenging, as you can only indirectly derive it. The basic idea is to apply a known test pattern to the receiver and to measure the transmitter's response.

The test consists of a suitable pulse-pattern generator that generates the stimulus signal, training sequence TS₁. As sequences such as TS₁ may contain multiple megabytes of data, consider employing a straightforward-to-use pattern editor. For specific tests, a function generator complements the stimulus part to insert jitter-sinusoidal, for instance-into the pulse generator's output signal. To that end, you want a wide jitter-insertion bandwidth. On the response side, you can use either an oscilloscope or a logic analyzer. Alternatively, you could choose a bit-error-rate tester.

You conduct the stimulating training sequence under nominal conditions for the functional tests and superimpose stress for the stress tests (Figure 2). You apply stress to the DUT (device under test) by using various levels and swing, adding noise to the levels in common and differential mode, or adding jitter to reduce the eye opening.

The receiver-compliance tests that the PCI Express standard specifies comprise receiver-voltage, jitter-tolerance, common-mode, and crosstalk tests. You conduct the basic receiver-voltage test by applying a defined training sequence (pulse-generator output) to the PCI Express receiver and measuring the response of the transmitter with a logic analyzer or an oscilloscope. The test generates the signals both with the minimum specified voltage swing and then again with the maximum allowed voltage swing. The system achieves compliance when the DUT responds with the expected sequence in both cases.

The definition of "jitter" is the short-term variation on the zero-crossing time from the ideal position in the time domain. A reference clock that you recover from the data stream gives the ideal position. The reference has to track the spread-spectrum clock and wander, but not jitter. You perform reference-clock extraction using either hardware or a software phase-locked loop. For the jitter-tolerance test, you basically conduct the receiver-voltage test with random noise, sinusoidal jitter, or both, superimposed on the training sequence. You achieve the jitter injection by appropriately combining the output signals of a function generator and a pulse generator. To that end, you apply a standard function-generator waveform, such as a sine, triangle, or square, to the pulse-pattern generator's jitter-insertion port (delay-control input). The bandwidth of the pulse-pattern generator's jitter-input port needs to be adequate. You determine the receiver's jitter budget by adjusting the jitter amplitude until the device no longer generates the expected response.

The common-mode compliance test again comprises a pulse generator, a function generator, and an oscilloscope. This test adds common-mode noise to the nominal stimulus signal of the pulse-pattern generator by again using a function (noise) generator and the help of a power combiner. You achieve compliance in case the DUT responds with the expected data output.

Finally, the crosstalk-on-idle test requires the same instruments as in the other tests. This test, however, applies only single-ended noise on a transmission line adjacent to the tested one.

For more details on PCI Express receiver-design-validation tests, such as those on the generation of pre- and de-emphasized signals, see Reference 1 . You can also find information on jitter measurements at Reference 2 . For further information on advanced jitter analysis with wide-bandwidth sampling oscilloscopes (communication analyzers), see Reference 3 . These references also cover total-jitter measurement as well as the separation of jitter into random and deterministic jitter.

Engineers use SATA for connecting disk drives to motherboards or host adapters. The data-transfer rate of first-generation SATA (Generation I or SATA-I) is 1.5 Gbps. The equivalent data rate is 150 Mbytes/sec. SATA-II runs at twice that speed: 3 Gbps and 300 Mbytes/sec. The first devices recently became commercially available. SATA-III will run at 6 Gbps (600 Mbytes/sec).

You use compliance tests to guarantee the signal quality (eye pattern, jitter), out-of-band signaling, ac/dc common-mode voltage, and receiver sensitivity (squelch test). The tests are similar to the PCI Express ones; therefore, the test-equipment requirements are similar. The recommended equipment again comprises a pulse-pattern generator, a function generator, and an oscilloscope. Test-equipment vendors offer comprehensive-sometimes free-SATA-compliance-test software. The software can run on the oscilloscope and can control the pulse-pattern generator.

Figure 3 provides an example for a specific SATA-compliance test. The figure shows screen shots of commercially available SATA-test software running on a high-speed, real-time oscilloscope after a successful transmitter-compliance test. The system passes the test if the transmitted test pattern does not violate the given mask. For the SATA protocol, out-of-band signaling is particularly important. You conduct out-of-band-signaling tests to ensure that the host and the device properly establish communication. You use so-called beacon signals to initialize the link between a host (the PC) and its client (the hard-disk drive) for this test. This test sends multiple data bursts to the DUT for different device states. The bursts always contain the same data. The bursts differ only in their signal-to-pause ratio, and user-friendly pattern editors can easily generate them. The compliance tests send all possible out-of-band signals to the DUT with the beacon-to-pause ratio set to both the maximum and the minimum allowed ratio for each state. In addition, this test checks the behavior of a DUT for a ratio outside the specified range. As in the PCI Express tests, this test monitors the reply data of the DUT's transmitter to determine whether it properly received the stimulus signal.

Figure 4 depicts an example of an out-of-band-signaling test. The top signal trace displays the pulse generator's stimulus signal. The traces below show the response of the DUT in single-ended and differential displays. In this example, the DUT properly responds to an initialization sequence that is in line with the specification.