FROM EDN EUROPE: PLD architecture bridges CPLD, FPGA applications

Lattice Semiconductor's newest series of programmable logic devices will suit applications for which designers previously specified either the largest CPLDs, or parts from the low end of one of the FPGA series. The manufacturer based these devices on relatively conventional 4-input, look-up table (LUT) logic elements. They employ flash memory for configuration storage and also include distributed block memory. In size, the parts have been designed with 256, 640, 1200, or 2280 LUTs. Lattice has employed a structure introduced in a previous series, which it calls TransFR, that uses a dual-memory arrangement. When you load the logic configuration into the chip, it is held in flash memory. However, the logic array itself is SRAM-based—at power-up, the configuration is transferred from the flash to the SRAM in milliseconds. The contents of either SRAM or flash may be changed while the device is in operation, allowing in-service configuration upgrades.

Called the MachXO ("XO" for "cross-over", to convey the market positioning of the series between CPLD and FPGA), the technology offers pin-pin delays of as little as 3.5 nsec (Picture). Core voltage is 1.2V—one version of the product runs at this supply level, or alternatively you can use an on-chip regulator to interface with 1.8, 2.5, or 3.3V systems. Depending on size, chips have one or two analogue PLLs, and one to three embedded RAM blocks of 9.2 kbits each. Developers can also load embedded memory contents from the flash array, so that in addition to using it as single- or dual-port RAM, they can configure it as user ROM. In addition to the block memory, around one-quarter of the programmable function units on the chips have distributed memory associated with them. The PLLs operate over 25 to 375 MHz, with low jitter, are programmable in phase and duty cycle, and can dynamically adjust delay, ±2 nsec in steps of 250 psec. A low-power mode reduces current demand to under 100 µA—SRAM contents are lost during this power-down, requiring a re-load from the flash array on recovery.

Lattice says that the family combines the fast pin-pin signals, high I/O-to-logic ratio, and "instant-on" features of CPLDs, with the register-rich, distributed-memory attributes of FPGA. The MachXO parts will sell for at $1.50 and $2.25 (250,000) for the two smallest parts in the range, and the company will announce pricing for the larger devices later. Tool support is available in the company's ispLEVER package, including routines for implementing in-service configuration upgrades.

Lattice Semiconductor, www.latticesemi.com.