FROM EDN EUROPE: Stable PLL synthesises fast clocks

For applications that require a clock with good stability in both long-term (frequency stability) and short-term (phase noise and jitter) parameters, designers will often specify a crystal oscillator. If the frequency of operation is a non-standard one, this may mean a custom design with a long lead time. ON Semiconductor's claim for its NB4N507A chip is that it can replace many such crystal oscillators while maintaining jitter performance. The NB4N507A is an integrated PLL (phase-lock-loop) that generates a frequency from 50 to 200 MHz from a low-cost reference crystal. It has a maximum RMS jitter figure of under 10 psec, which is less than half (according to ON) that of alternative solutions. The company builds the device using a fully differential bipolar technology that gives a PECL (positive emitter-coupled logic) output with a duty cycle of 50% ±2%, and specifies stability of 100 ppm (parts per million). The chip requires a crystal to provide the input reference in the 10–27 MHz range, and generates an integer multiple of that reference at its output. The part is suited for use in SONET and other communications applications, and can produce a precise 155.52 MHz clock from a 19.44 MHz crystal by ×8 multiplication. It has a loop bandwidth of over 10 kHz and will track any modulation on the input up to 10 kHz—designers can therefore use it as a high-frequency VCXO (voltage-controlled crystal oscillator). The chip costs $1.50 (1000).

ON Semiconductor, www.onsemi.com.