Big thermal challenges come in small packages

To ensure system reliability, thermal evaluation is a requirement with any size IC. A few simple calculations can help designers estimate and evaluate the thermal behavior of ICs, and lab testing verifies the calculated conclusions.

Consider a dual-LDO (low-dropout) regulator in a DFN8 (eight-pin, dual-flat no-lead) package. Dual LDOs convert one battery input voltage to two lower output voltages with approximately twice the power dissipation of one LDO. In addition, smaller-package DFN8 LDOs have lower thermal resistance than their larger counterparts.

In Figure 1a, with an input voltage of 4.2V, regulator 1 (LDO₁) inside the DFN8 package generates an output voltage of 2.8V at 300 mA output current (typical), and regulator 2 (LDO₂) generates an output voltage of 1.8V at 150 mA (typical). The dual-LDO power dissipation is 780 mW. The maximum allowable steady-state junction temperature for the dual LDO is 125°C.

The data-sheet specification for the junction-to-ambient thermal resistance (R_θJA) of the DFN8 package is 41°C/W. The four-layer test method in the JEDEC JESD51-5 and JESD51-7 standards defines the DFN8 thermal resistance. In the JESD51 specifications, some conditions of the test are four-layer boards with a copper thickness of 2 oz on the outer layers and 1 oz on the inner layers.

The model in Figure 1b shows the elements for a first-order thermal calculation. In this model, power is the current source, temperature is the voltage, and thermal resistance is a resistor. The definitions of the variables are as follows: I_SOURCE is the power in watts, T_J is the chip junction temperature in degrees Celsius, T_C is the device case temperature in degrees Celsius, T_A is the ambient temperature in degrees Celsius, R_θJC is the thermal resistance from the chip junction to the device case in degrees Celsius per watt, R_θCS is the thermal resistance from the device case to the copper ground plane (pc board) in degrees Celsius per watt, and R_θSA is the thermal resistance from the device copper ground plane to ambient (air) in degrees Celsius per watt.

If the dual LDO dissipates 780 mV, the rise in temperature at the junction above ambient of the dual LDO is T_J(RISE)=32°C, using R_θJA of 41°C/W. The reliability requirement limits the maximum ambient temperature to (125–32°C), or 93°C.

A feasible two-layer layout for the dual LDO shows different results. For example, consider a board with a 0.0625-in. FR4 substrate and 1-oz copper traces, with the traces residing on the top layer and the copper ground plane on the bottom. Using this pc board, the junction-to-ambient thermal resistance (R_θJA) is 78°C/W.

Measuring thermal response with this type of board proves that the rise in temperature under full-load conditions of the dual LDO increases from 32°C (four-layer with vias) to 59°C. Under these conditions, the maximum ambient temperature is (125°C–59°C), or 66°C. This temperature difference is primarily due to lack of internal layers and vias directly into the copper plane, as the JEDEC standard defines. Thus, although data-sheet specifications are accurate, the physical implementation of the product on the pc board weakens the device's thermal performance.