Interleaving dc/dc converters boost efficiency and voltage

Boost power supplies are popular for creating higher dc voltages from low-voltage inputs. As the power demands from these supplies increase, however, a single power stage may be insufficient. This article presents an interleaved-boost approach, which, compared with a single-boost converter, both analytically and empirically provides efficiency, size, and cost advantages. The article also compares test results of 250W, single-phase and interleaved-boost power supplies. The interleaved-boost topology provides superior performance, albeit with increased complexity.

The motivation for the work this article describes was the selection of a power-supply topology for an ink-jet printer's solenoid driver. The input voltage was 12V dc; the required output was 37V dc at 7A. The supply's input current could exceed 20A. It was initially unclear whether a single power stage or a multiphase stage was most appropriate. As in buck regulators, currents could be high enough to make duplicate power stages desirable; they spread the dissipated heat around the pc board and reduce the stress on many of the circuit components. The work discussed included evaluation of single- and two-phase-boost topologies.

Table 1 presents the power-supply requirements. To maintain the desired output voltage within a small margin, this supply is subject to substantial current surges as the solenoid energizes and de-energizes. In addition, high efficiency is important for maintaining an acceptable temperature rise. The 37V, 7A output delivers more than 250W to the load. Even with an efficiency of 91%, the power supply dissipates 25W, requiring multiple heat sinks. Moreover, the supply's size and cost were important, although no specific requirements were provided.

Figure 1 compares two power supplies. The top supply is the single-phase design with a single input inductor. The circuit below it is the two-phase design. The single-phase design requires approximately 18 in.² of pc-board area, whereas the interleaved design requires 14 in.² The largest differences in area between the two approaches are in the inductors, output capacitors, and heat sinks. The maximum height of the interleaved inductors is also less than that of those in the single-phase design.

Figure 2 shows the schematics of the single-phase- and interleaved-boost converters. In the single-phase design, applying a gate voltage to FET Q₁ pulls the drain potential to ground, applying the input voltage across inductor L₁ and causing current to ramp up. During the ramp time, output capacitor C₂ must alone supply the load current. When Q₁ turns off, the voltage across L₁ reverses polarity to maintain current flow. This scenario forces the switch node more positive than the input voltage and forward-biases diode D₁, charging output capacitor C₂ and supplying the output current. For each of the two switching states, the inductor's volt-microsecond product must balance. That is, d/f_S×V_IN=(1–d)/f_IN×(V_OUT–V_IN), yielding the relation V_OUT=V_IN/(1–d), where d is the duty ratio, f_S is the switching frequency, V_IN is the input voltage, and V_OUT is the output voltage. This expression is valid in CCM (continuous-conduction mode), in which the inductor current remains positive at all times.

Each phase of the interleaved-boost converter (Figure 2) works in the same way that this single-phase-boost converter does. The two power stages operate 180° out of phase, canceling the ripple current in the input and the output capacitors. The interleaved-boost approach uses forced current-sharing between the power stages to equalize the power that the stages deliver. Without this feature, one power stage could deliver substantially more power than the other, which would defeat the ripple cancellation.

Figure 3 shows how interleaving benefits input-capacitor ripple-current cancellation. The two power stages operating 180° out of phase provide a two-to-one reduction in peak-to-peak ripple current. Because the interleaved-boost converter's combined input-ripple current equals that of the single-phase converter, the two-phase design's individual-phase ripple currents can each be twice as large as that of the single-phase design. The individual interleaved power stages operate at the same frequency as the single-phase design, 100 kHz, but the effective input- and output-ripple frequency is 200 kHz. The interleaved-design calculation used a frequency of 100 kHz and twice the ripple current of the single-phase design, yielding half the inductance. Because the two-phase design's effective input-capacitor ripple current was the same as that of the single-phase design, the two designs used an equal number of input capacitors. Ripple cancellation allows a choice of which components to reduce in number. Using two inductors, each having the same value as that in the single-phase design, halves the input-capacitance requirements. In a boost design, however, the inductor requirements are generally more critical than those of the input capacitors.

Interleaving benefits the output capacitors in about the same way as it affects the input capacitors. Figure 4 shows the single-phase output-capacitor ripple current. In this design, this waveform's rms current is approximately I_PP×(d×(1–d)), or 10A rms. The inductor slope, which appears at the top of the waveform, does not significantly add to the total rms current. This capacitor supplies all of the output current during the FET's on-time. During the off-time, however, a current of I_OUT×d/(1–d), or 14A, flows into the capacitor to recharge it. In designs that use aluminum-electrolytic output capacitors, capacitor ripple-current ratings determine the required number of capacitors.

Figure 5 shows the interleaved-boost converter's individual and combined output-capacitor currents. Not counting the inductor slope, the phase A and B currents' peak-to-peak amplitudes are half those of the single-phase design because the duty cycle of the current flowing into the output capacitors is twice that of the single-phase design. In Figure 5, the rms value of the combined or total waveform is 5A, allowing half the number of output capacitors to maintain a ripple voltage no greater than that of the single-phase design.

Figure 6 shows the ripple-current cancellation that you can obtain at various duty cycles. The vertical line indicates the operational duty cycle and shows the interleaved-boost circuit's two-to-one rms-current reduction compared with that of the single-phase circuit. A 50% duty cycle can provide perfect cancellation.

Figures 7 and 8 show the completed single-phase- and interleaved-boost-converter designs. In the single-phase design, a UCC38C43 PWM (pulse-width-modulation) controller operating in voltage mode drives a pair of MOSFETs. Because the boost converter offers no way to limit the output current in the event of a short circuit, a TPS2490 hot-swap circuit with overcurrent protection was added during testing to halt current flow during overcurrent faults. Figure 8 illustrates the interleaved design using a UCC38220 dual-interleaved PWM controller. Low-cost transformers in the drain leads of Q₅ and Q₇ sense the FET current. The controller forces equal current in the two phases. Reduced current in the rectifiers eliminates the need for heat sinks and lowers assembly costs.

The above scenario compared the two designs for efficiency, input- and output-ripple voltage, and transient loading. In most situations, the two-phase approach exhibited better performance than did the single-phase approach. Figure 9 compares the efficiency of the two approaches. Both meet the target 91% efficiency; however, at full load, the two-phase approach's efficiency is more than 2% better. Although this improvement may sound insubstantial, the difference in losses between the two supplies is significant. The single-phase design dissipates 23W, whereas the two-phase approach dissipates only 16W, significantly affecting the choice of heat sink and the thermal design.

The single-phase curve's early maximum and rapid decline indicate that the design has significant conduction losses. The big differences between the two designs are the losses in the inductor, boost diode, output capacitors, and pc board. Table 2 compares the inductor requirements and designs' performance. The two-phase approach uses significantly less inductance than does the single-phase approach, and each inductor carries half the current. Energy-storage requirements and temperature rise determine an inductor's volume. The formula ½×L×I² determines energy storage. Table 2 shows that the energy storage of the single-phase design is five times that of the two-phase approach. Therefore, if the temperature rise of the inductors had been equal, the single-phase inductor would have been five times as large.

Rather than keeping the energy density equal, the designers chose to allow a higher temperature rise in the single-phase design, sacrificing some efficiency by using an inductor with higher losses; consequently, losses in the single-phase design are about 5W higher. Output capacitors accounted for about 1W of the power-loss difference. Ripple current in each of the output capacitors produced about 100 mW of dissipation, and the single-phase approach needed approximately six more capacitors than did the two-phase design. The two-phase approach required the use of two diodes in the power stage, with each carrying half of the total current. Consequently, the diodes exhibited a lower voltage drop, resulting in approximately 1W less loss.

Figure 10 shows the input- and output-voltage-ripple measurements. Figure 10a is the single-phase converter, and Figure 10b is the interleaved converter. The upper traces, which show the output-ripple voltage, illustrate several key points. The inductor current flowing through the output capacitor's ESR (equivalent series resistance) mainly determines ripple voltage. The traces in Figure 10b show the higher frequency ripple that the interleaved approach achieves. In Figure 10a, the top of the ripple is nearly flat because of the large value of the boost inductor. In Figure 10b, the slope is significant because of the large change in inductor current during the power-switch off- time. The lower traces also show the input-ripple voltage's higher frequency with the two-phase approach.

Just as with buck regulators, interleaved-boost regulators can provide performance benefits over single-phase designs. Table 3 compares the completed single-phase-boost design with the interleaved-boost approach. The interleaved-boost circuit is smaller, shorter, and more efficient. The fact that it has fewer output capacitors is largely due to lower output-ripple current, which results in lower cost and lower power dissipation. This circuit also significantly reduces the energy-storage requirement of the combined input inductors, thus reducing the magnetic volumes, heights, and dissipations. The multiphase approach reduced the overall power dissipation by 30% and spread that dissipation over a larger board area, allowing better thermal management. The main drawback of the multiphase approach is added circuit complexity, requiring measurement and balancing of each phase current as the larger number of control components illustrates.