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No SOC is an island

Designers must look beyond the confines of the SOC and pay attention to integration with external chips and systems.

By Gabe Moretti, EDA consultant -- EDN, 7/21/2005

Advances in semiconductor technology have made it possible to fabricate millions of transistors on one die. Engineers have taken advantage of this capability to implement processors, memory blocks, and peripheral devices on the same IC. The industry calls such designs SOCs (systems on chip).

However, the chip alone is never a complete system; in every instance, engineers must consider necessary integration with other chips and systems outside the SOC. Meanwhile, the high degree of on-chip integration is stressing the capabilities of on-chip buses, since the vast majority of designs now require the transfer of increasingly large amounts of data between various processing blocks with the highest possible efficiency.

As a result, the problem of transferring data on and off the chip often gets downplayed and handled in a less than optimal manner. For example, designers cannot find nearly as many EDA tools that deal with such issues as they can find tools for the lower levels of chip design and analysis. Even providers of IP (intellectual property) blocks tend to focus on the problems inside the design—choosing to highlight integration at the expense of system-level design and verification.

Much, if not most, of the off-chip data traffic occurs between the chip itself and external memory and storage devices. Memory controllers present particular challenges due to the variety of memory types that are available today. Most portable devices incorporate SDRAM (synchronous DRAM) and NOR flash memories. But leading-edge designs are now also using DDR-DRAM (double-data-rate DRAM), NAND flash memories, and, in some cases, SFF-HDDs (small-form-factor hard disk drives).

Portable products must be sensitive to power issues, and specialized DRAM memories now offer dozens of features for low-power modes. This creates a design challenge when you consider the short development time required to hit the market window for devices such as cell phones. System designers have traditionally considered memory chips as commodity devices, so memory controllers have not received the attention they now command. As a result, very few design teams have the resources or experience necessary to develop an efficient memory controller that extracts the necessary performance from leading-edge memory devices, be they dynamic or nonvolatile devices.

The functionality of portable devices is getting so sophisticated that in addition to new memory requirements, they now require storage for large amounts of data. Disk manufacturers are responding to the challenge with SFF-HDDs that fit in cell phones. These new drives use the recently developed CE-ATA (consumer electronics ATA) protocol, which leverages the existing MMC (multimedia card) flash-card interface specifications to minimize pin counts and protocol complexity.

Engineers now need to need to consider integrating CE-ATA controllers into their SOCs, as well as controllers for flash and DRAM devices. To date, design teams have generally handled the design and verification of controllers for flash and DRAM separately, usually at the expense of increased verification costs and sub-optimal system performance. Today, given the need for storage, combined with requirements for even lower power and higher data-transfer rates, it behooves design teams to look at DRAM, flash, and storage as a data subsystem. The same points are true for non-mobile systems, except that designers would implement a Serial ATA (SATA) interface to the hard drives instead of CE-ATA. In both cases, the availability of proven and trusted IP blocks that integrate the control and management of off-chip memory and storage can save significant verification time and reduce time-to-market.

Unfortunately, most IP blocks, with the exception of the PCI Express cores available from a few suppliers, focus on the inside of the IC, not on external resources. Another exception is Dataplex, from Denali Software, an IP block that aims to ease the engineering task of integrating off-chip memory and storage resources with the SOC.

Dataplex is a configurable subsystem that designers include in an SOC to implement interfaces to off-chip memory and hard-disk-storage devices. The product aims to offload some of the traffic from the system bus inside the IC and also provide a tested and flexible solution to integration of memory and storage controllers into an efficient data subsystem.

Just a few weeks before this product's introduction, Bernard Meyerson, an IBM Fellow who is vice president and chief technologist of IBM's systems and technology group, called for a holistic approach to system design during a keynote address at the 42nd DAC (Design Automation Conference). Considering the entire system, not just what is on the chip, is an example of holistic system design.

Gabe Moretti is an EDA industry veteran (and former EDN technical editor) who now does consulting work for a variety of EDA-industry players, including Denali Software.