FROM EDN EUROPE: Logarithms-the new floating point?

From a university spin-off company in the North of England comes a microprocessor that is claimed to be the first to operate directly on numbers that it holds in a logarithmic representation. The device is aimed at applications that involve heavy computation loads, and would essentially replace today's floating-point processors or co-processors. It's designers say that it offers a performance gain in such mathematically-intensive algorithms.

When numbers are represented as logarithms, multiplying or dividing two numbers is carried out by addition or subtraction. Clearly, this offers the possibility of simplifying the multiplications that lie at the heart of many DSP or graphics algorithms. However, while the processes of multiplication and division are simpler, addition and subtraction become correspondingly more complex. According to Northern Digital, although the concept of a logarithmic processor has been considered before, it has never been thought worthwhile to implement it. By designing a computation architecture that overcomes this problem and carries out logarithmic addition and subtraction efficiently, the new company has been able to demonstrate an overall gain in arithmetic performance.

Floating-point numbers are usually represented as an 8-bit exponent and a 23-bit mantissa. Using the same register space, the equivalent logarithmic representation is an 8-bit integer part plus a 23-bit fractional part. The basic accuracy is the same; however, over the many repeated cycles that characterise computation-intensive tasks, accuracy is better than in the floating point case, because the rounding errors involved at each step-which accumulate as a calculation proceeds-are less.

Northern Digital's processor uses slightly fewer machine cycles to carry out addition and subtraction than a conventional (IEEE-754) floating-point unit (FPU). But whereas an FPU might complete a single multiplication or division in 30 or 40 cycles, the logarithmic processor needs only one. This factor underpins the company's assertion that the machine will suit advanced DSP and graphics algorithms: with a 4-stage pipeline, latency is also low. In particular, the company says that the design will immediately run emerging and experimental DSP algorithms efficiently, without the effort that is often needed to tune their code for a conventional, floating-point, machine.

The company built a prototype in 0.18-micron CMOS, which runs at 125 MHz; it is available on an evaluation board that interfaces to a host system via a serial interface, backed up by assembler software and a mathematical function library. Northern Digital is developing a C-compiler. It intends to operate as both a fabless semiconductor company and an IP source.

Northern Digital, contact j.n.coleman@ncl.ac.uk.