FROM EDN EUROPE: ΣΔ ADCs use under 100 mW at 40 MHz and 14 bits

"The lowest power delta-sigma analogue-to-digital converters available anywhere," is the claim of fabless semiconductor vendor Xignal Technologies. It bases its product concept on an architecture it calls continuous-time sigma-delta. Resolutions of 12 bits and above can now be realised at power levels under half that of pipeline ADCs, says Xignal's marketing director Mark Holdaway. A sigma-delta converter is a control loop in which a comparator samples the output of an integrator to yield a pulse-density output waveform. Integral to that loop is a filter which in a conventional sigma-delta design is a discrete-time arrangement that depends on switched-capacitor techniques. Xignal's design replaces this with a continuous-time digital filter, taking switches out of the signal path. The analogue circuitry in the design is simplified, eliminating several functional blocks such as an input buffer that previously dealt with sampling glitches. Key to the design is the integration of high-stability inductors and capacitors, and a PLL that delivers clocking with very low phase noise. The architecture makes the ADC compatible with the scaling benefits of small-geometry CMOS, further assisting the power benefits that flow from reducing the power-hungry analogue blocks in the design. With the digital filter outside the conversion loop of the ADC, the architecture also eliminates a separate anti-alias filter. Using the IEEE's formula for figure-of-merit relating power per bit of conversion resolution and conversion frequency, Holdaway says the CT sigma-delta achieves a figure double that of previous ADCs.

Hence, the XT11 series of 12- and 14-bit self-clocking ADCs that use 70 mW while clocking at 20 to 40 Msamples/sec. They are simple to drive, needing no differential input buffer; the continuous-time loop filter can handle "beyond-the-rails" inputs, enabling the XT11200 and 11400 to accept ±4V inputs while operating from a 1.2V supply. The continuous-time sigma-delta modulator is a third-order design, and tunable loop filter plus digital low-pass filter are also integrated on-chip. The chips can sample the entire bandwidth to the Nyquist limit (20 MHz for a 40-MHz clock) with virtually no wasted bandwidth. SNR is 76 dB, and THD is –82 dB (for the 14-bit part-the corresponding figures for the 12-bit converter are 71 and –78 dB). Holdaway adds, "The architecture has been used in single-sample-rate applications such as wireless base stations." As there are analogue elements determining bandwidth, the operating-frequency range of a given implementation is limited but, according to Xignal, to a range of frequencies, rather than a fixed frequency of operation. The on-chip, low-phase-noise clock requires only a low-cost crystal. In 1000 quantities the converters will sell for $9.95 or $18.00.

Xignal, www.xignal.com/xt11.