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IP and EDA startup wants to make SOCs asynchronous
By Michael Santarini, Senior Editor -- EDN, 12/19/2005
Silistix, an IP-bus and EDA startup originating from research performed by the University of Manchester and funded by Intel Capital, wants to help you make the next generation of SOCs (systems on chips) asynchronous.
Most ASICs and SOC architectures today are synchronous, with every component in the design functioning at the command of a single system clock. As process geometries continue to shrink and gate counts continue to climb, timing closure will become an increasingly difficult task, according to Silistix vice president of marketing David Fritz.
To get around clock-related problems, Silistix (pronounced Sill-is-ticks) is introducing this week its asynchronous packet-based bus called CHAIN (an acronym somewhat inventively created from CHip-Area INterconnect). Users will specify the IP they want to use in their SOC and upload HDL blocks, then use Silistix's synthesis tools to generate a CHAIN bus that interconnects the blocks that make up the design.
"We can reduce design effort in a couple of significant ways," Fritz said. "Since there is no system clock coming into the interconnect and no critical path coming out of any of the endpoints into the interconnect and back out to another endpoint, timing closure becomes very simple. You get timing closure for each of your endpoints—an MPU, DSP, or memory-controller block—then timing closure on our CHAIN interconnect, which is simple because there is no system clock, and your timing closure is done. You don't have to worry about clock skew, clock balancing, or clock jitter. All those timing-related issues that pop up in the latter part of the design phase go away."
The technology was developed by John Bainbridge and Andrew Bardsley, both of whom received their PhDs under the tutelage of University of Manchester professor Steve Furber, noted for developing the ARM architecture. Since developing the ARM architecture, one of Furber's many projects has been trying to come up with a viable asynchronous IC architecture, Fritz said. A few years back, Furbey directed Bainbridge and Bardsley to the problem. Bainsbridge developed the hardware architecture for CHAIN, while Bardsley developed the synthesis tool set to generate the bus. Bainsbridge's PhD dissertation on CHAIN's predecessor, the MARBLE asynchronous system bus, won the 2001 British Computer Society/CPHC Distinguished Dissertation Competition.
Meanwhile, Bardsley at UoM was the architect and developer of the Balsa synthesis system, an asynchronous equivalent of Design Compiler from Synopsys, which has been used in the development of self-timed versions of ARM cores. "He pioneered the process of synthesizing an asynchronous circuit from HDL," Fritz said.
The three recruited EDA industry vet Roy McGuffin, former CEO of Cadence-purchased Antrim Design Systems, to be Silistix's CEO. The company now has 25 employees and is in the process of establishing a headquarters in San Jose.
While the company is talking about the CHAIN bus, it isn't disclosing details of its CHAINworks tool set until January. Fritz did say, however, that the tools will be used after design entry but before logic synthesis. The tools will work with traditional EDA tools. They will accept Verilog and SystemVerilog as inputs and SystemC in future releases. Users will input IP blocks and specify constraints, and the tool will automatically generate the CHAIN bus that links the different blocks together.
"What you'll get in CHAINworks is a tool that will help you design and optimize your interconnect and a synthesis tool to generate self-timed circuits to implement the interconnect," Fritz said. "What gets generated is a fine-grained topology. You get to define the topology based on lots of criteria and it allows you to control the balance between performance, area, and power of the interconnect. Portions can have very wide pipelines. Others can be very slow and narrow if, for example, you want to communicate with a UART. We don't try to force you into a topology like crossbar or hierarchical structure. You can use our tool to create any of those or any combination of those."
Silistix accommodates GALS (globally asynchronous, locally synchronous) design architectures. So, for example, if users already have a block that runs on ARM AMBA, the tool can generate an adaptor that allows that subnetwork (block running on AMBA) to be incorporated with the rest of the design running on the asynchronous CHAIN.
The CHAIN architecture currently supports the AHB and APB IP protocols, and the company is working on adding support for AXI and OCP-IP. It also supports STMicroelectronics' STbus. The company also has adaptors that allow users to plug in IP blocks that are not currently preconfigured/supported in the CHAIN system.
The CHAINworks tool set runs on a proprietary library called the CHAINlibrary. Rather than having multipliers and adders, as you would find in a Synopsys DesignWare library, the library contains components used to construct self-timed interconnect. "They can be mapped to any process that you'd like," said Fritz, who noted the components can also be manually optimized to tailor the product even more to a given process and geometry.
Implementing CHAIN does take up more area than a synchronous-bus-based architecture, but customers don't have an issue with that, Fritz said. A future version of CHAINworks will support a BIST controller to reduce the area impact.
Intel Capital has been an investor since 2003, Fritz said. Intel is also rumored to be using to the tool on a current design project. No commercial silicon has been produced with the tool yet, Fritz said, but the technology has been proven on silicon run during research at the University of Manchester.
Customers will be able to license CHAIN bus and the CHAINworks tools together with an annual subscription.
Silistix isn't the first company to try to commercialize an asynchronous bus and tool chain. Fulcrum Microelectronics, a spin out of the California Institute of Technology, introduced a similar technology in 2003. The company's sales model didn't take hold, but Fulcrum has had some success making its own asynchronous chips using its technology.
The Silistix approach will be a strong commercial offering because of its strong EDA tools, the company's sales model, and the fact that CHAIN is not a fixed crossbar-switch topology, Fritz said.
