Accent, ARM and Cadence Collaborate on Low-Power Design

Online staff -- Electronic News, 7/25/2005

ARM and Cadence Design Systems Inc. said today that SOC design services firm Accent has validated a low-power design flow using Cadence’s Encounter digital IC design platform and ARM’s Artisan physical IP.

The design flow targets low-power IC design and was proven on a design comprising a large portion of a SoC for a wireline application.

Using the ARM Artisan Metro low-power IP with multi-voltage and multi-threshold capabilities, the design was implemented with a multi-supply multi-voltage (MSMV) design flow utilizing three power domains. High voltage threshold (low leakage) optimization was performed on both the MSMV implementation and a baseline implementation with a single supply voltage to further reduce leakage power, the companies said.

Compared to the baseline design flow, the companies claim the low-power design flow reduced dynamic power by 34 percent. Additionally, the low voltage section of the design also showed 40 percent less leakage power than the baseline flow implementation so that Accent was able to perfect a methodology that implements multi-voltage capabilities in new designs and to compute trade-offs in power consumption.

“The need to accommodate multiple power domains and multiple voltage levels makes low-power chip design much more complex than normal chip design,” said Claudio Fasce, VP of business area design and supply chain management services for Accent, in a statement.

“Using the Cadence Encounter platform and the ARM Metro IP supporting MSMV design, we were able to quickly validate our low-power design flow and significantly improve our overall low-power design methodology,” he continued.

“Close collaboration with ARM and Cadence expands our design skills and enables us to deliver better performing devices and a greater competitive advantage to our customers,” Fasce added.

The Encounter low-power flow supports multiple supply voltage designs, and contains top-down multi-supply voltage synthesis using Encounter RTL Compiler global synthesis. This is followed by Encounter implementation for low-power and accurate SI- and IR-aware timing sign-off with CeltIC Nanometer Delay Calculator (NDC) and VoltageStorm static and dynamic power analysis, Cadence said.

Wei-Jin Dai, platform VP for digital IC implementation at Cadence explained that the project demonstrates the production readiness and quick turnaround capabilities of the Encounter low-power design flow. “Through our broad, deep collaboration with design chain leaders such as ARM and leading-edge design houses such as Accent, we are able to continue advancing low-power design into the mainstream,” he said.

Further, the ARM Artisan Metro low-power platform provides dynamic and leakage power reduction, and makes high-density, yield-improved designs possible. The platform includes standard cells, memories, I/Os and multi-voltage kits. All components take advantage of new process, circuit design, voltage scaling, power-aware EDA and chip-level design techniques to allow for power dissipation control.

Cadence also announced today a new version of its Allegro system interconnect design platform meant to shorten design cycle time by enabling team-based PCB system design throughout the design flow.

The entire Allegro product line has been enhanced with greater productivity and ease-of-use capabilities, Cadence concluded.