"The lowest power delta-sigma ADCs available anywhere" is the claim of fabless-semiconductor vendor Xignal Technologies. It based its product concept on an architecture it calls continuous-time delta-sigma. With it, designs can achieve resolutions of 12 bits and higher at power levels less than half those of competing ADCs, says Xignal's marketing director, Mark Holdaway. A sigma-delta converter is a control loop in which a comparator samples the output of an integrator to yield a pulse-density output waveform. Integral to that loop is a filter, which, in a conventional sigma-delta design, is a discrete-time arrangement that depends on switched-capacitor techniques. Xignal's design replaces this technique with a continuous-time digital filter, taking switches outside the signal path. The approach simplifies the device's analog circuitry, eliminating the need for several functional blocks, such as an input buffer that previously dealt with sampling glitches.

The design integrates high-stability inductors and capacitors and a PLL that delivers clocking with very low phase noise. The architecture makes the ADC compatible with the scaling benefits of small-geometry CMOS, further assisting the power benefits from reducing the power-hungry analog blocks in the design. Because the digital filter is outside the conversion loop of the ADC, the design also needs no separate antialiasing filter. Using the IEEE's formula for figure of merit relating power per bit of conversion resolution and conversion frequency, Holdaway says, the CT sigma-delta achieves a figure double that of previous ADCs.

Hence, the XT11 series of 12- and 14-bit, self-clocking ADCs use 70 mW while clocking at 20M to 40M samples/sec and are simple to drive, needing no differential input buffer. The continuous-time loop filter can handle "beyond-the-rails" inputs, enabling the XT11200 and 11400 to accept ±4V inputs while operating from a 1.2V supply. The continuous-time sigma-delta modulator is a third-order design, and the chip also integrates a tunable loop filter plus a digital lowpass filter. The chips can sample the entire bandwidth to the Nyquist limit—20 MHz for a 40-MHz clock—with virtually no wasted bandwidth. SNR is 76 dB, and THD is –82 dB for the 14-bit part; the corresponding figures for the 12-bit converter are 71 and –78 dB.

"The architecture has found use in single-sample-rate applications, such as wireless base stations," says Holdaway. Because analog elements determine bandwidth, a given implementation has restricted operating frequency. Xignal says that this limitation implies operation over a range of frequencies, rather than a fixed frequency of operation. The on-chip, low-phase-noise clock requires only a low-cost crystal. The converters will sell for $9.95 or $18 (1000).

Xignal, www.xignal.com/xt11.