FROM EDN EUROPE: Processor modeling supports concurrent development

Concurrent design has long been an objective of vendors supplying development tools to the embedded design community. Designers could greatly speed up the design process if they could develop embryonic code on a virtual model of the final hardware, without software de-signers having to wait for a physical prototype of the system to be built. To develop useful software, the virtual representation of the hardware has to be accurate (preferably completely cycle-accurate): but a detailed model of a hardware system written in conventional language will run too slowly for code developers to do useful work. To get usable speed, tool vendors must employ some sort of abstraction of hardware behaviour. The effort to achieve a truly useful compromise between speed and accuracy has been the story of this branch of the EDA industry.

Currently claiming to have squared that circle is VaST Systems, justifying its assertions with a user list that includes many automotive- and consumer-product builders, especially in the Japanese market. VaST's tools model processors and other hardware—the company quotes cycle-accuracy of typically 97-98% for models that run at 40 MIPs on standard computer hardware (no hardware acceleration is involved). Underlying the tools is a proprietary modeling language—but this is hidden from the user, who sees a shell around device models in standard C. In the tool set, CoMET is an architectural exploration tool that—among other functions—allows system architects to develop virtual system prototypes from higher level representations, following an "executable specification" approach. The other major tool is METeor, a software development environment that hosts code on the virtual prototypes.

VaST is now engaged in making the technology for creation of models in its system more widely available. The process started with the release of a platform-creation tool which enabled users to assemble a system model from library blocks; and a peripheral device builder, that lets users create functions at that level. VaST is not yet ready to release tools that will enable users to model a complete processor—that capability will follow later—but the company's latest announcement is a "virtual processor model transformer". This tool will allow users to modify the instruction set of a "seed" virtual processor that the company supplies. A seed would comprise instruction set, micro-architecture, pipelining and other essential behavioural data. Developers apply the "transformer" tool to the model to add, modify or remove instructions. At a cost of $100,000 for a one-year licence, this is clearly not a tool for every user—VaST is attempting to proliferate the ability to produce models for processor variants into end-users who are in a position to build SoC ASICs, and into silicon-vendors with processor product lines. The company's aspirations are that their models become a routine deliverable along with a given processor variant.

At the end-user level, the VaST tool set has an entry point that is also around the $100,000 level—the CoMET tool costs $30,000 per seat, for example—and CEO Alain Labat acknowledges that "a certain level of complexity" is needed to justify use of the software. Models are available for processors from a list of sources that includes ARM, Intel, NEC, MIPS, Renesas, Freescale, Toshiba, DSP Group, and StarCore.

VaST, +44 1296 713113, www.vastsystems.com.