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An Engineer's Guide to DesignCon: Technical panels
By Staff -- EDN, 2/6/2006
This year's DesignCon will include a number of technical panels covering topics including digital and analog IC design, printed circuit boards, and FPGA (field programmable gate array) design.
The technical sessions kick off with a Monday evening panel called "Jitter and Its Challenges when Testing Serial Data Designs." The panel promises to give attendees insight into understanding and controlling jitter in high-speed systems, describing how an understanding of how to characterize the source of jitter is key to successful high-speed design.
Moderated by Chris Loberg, marketing manager at Tektronix, the panel features Maxtor Corp.'s Eric Kvamme, Agilent's Greg LeCheminant, Wavecrest Corp.'s Mike Li, LSI Logic's Mark Marlett, Intel circuit architect Andrew Martwick, Kalev Sepp of Tektronix, and Teraspeed Consulting Group's Ransom Stephens.
Concurrent with the jitter panel, another panel titled "How to Choose Bypass Capacitors" will feature industry experts giving a comparative view of some of the popular design methodologies used in selecting bypass capacitors. Moderated by Istvan Novak, Sun Microsystems senior staff engineer, the panel includes Dale Becker, IBM senior technical staff member; Altera's Larry Smith; and consultant Steve Weir.
If you're pondering whether to use an ASIC, structured ASIC, or FPGA for your next design, or trying to decide between a configurable processor and a standalone microprocessor core, Tuesday afternoon's "Strategies for Device Differentiation" panel may be useful. The panel will look at device differentiation choices in the face of a cost-conscious consumer market. The panel features Suresh Rajgopal, principal engineer at STMicroelectronics; Jasbinder Bhoot, senior director of marketing at eASIC; J. Augusto de Oliveira, vice president and senior fellow at Philips Semiconductors; Grant Martin, chief scientist at Tensilica; iSuppli's IP and silicon industry analyst Jordan Selburn; and Naveed Sherwani, CEO of Open-Silicon.
Also on Tuesday afternoon, Gartner Dataquest chief industry analyst Bryan Lewis will moderate a panel on "The Growing Impact of Power on SoC Design." Panelists include Brett Cline, vice president at Forte Design Systems; Kam Kittrell, general manager at Magma Design Automation; Rakesh Sethi, business director at Toshiba America; Ed Wan of TSMC; and Mobashar Yazdani, ASIC program manager at Hewlett-Packard.
The ubiquity of Ethernet technology will feature in a panel entitled "The Impact of the Ethernet Ecosystem on Backplane and System Design." The panelists, led by moderator Rick Merrit will discuss backplane design, board fabrication, and advanced signal conditioning, and have also been challenged to give overall capacity forecasts. The panelists are Brad Booth, director of advanced products at Quake Technologies; Agilent Technologies' David Cunningham; Joel Goergen, chief scientist at Force10 Networks; Adam Healey, technical staff member at Agere Systems; and JP Miller, distinguished technologist at Hewlett-Packard.
On Wednesday, DesignCon will have three afternoon technical panels. The first will look at the adoption and proliferation of the OpenAccess API (application programming interface), which allows disparate EDA vendors and customers to connect tools and more easily construct a cohesive design flow. Moderated by Si2's Sumit DasGupta, the panel features Rajit Chandra, founder and CEO of Gradient Design Automation; Timothy Ehrler, senior principal methodology engineer at Philips Semiconductors; Nanda Gopal, senior member of Gradient's technical staff; Michaela Guiney, co-chief architect of OpenAccess at Cadence Design Systems; and Joe Morrell, a chief architect at IBM.
The second Wednesday evening panel is entitled "Why Do So Many Chips Fail? A Panel Discussion on Design Verification." Moderated by Tom Anderson, director of technical marketing at Synopsys, the panel will look at verification problems and attempt to identify where design teams should be placing the most effort to better their chances of completing a design correctly in a single pass. Panelists include Sergio Camerlo, director of engineering at Cisco Systems; Ira Chayut, verification manager at nVidia; Tensillica's Grant Martin; consultant Kevin Normoyle; and Broadcom's Russ Vreeland.
The third Wednesday afternoon panel, "Embedded Capacitance and Embedded Capacitors: Technology Progress and Applications" features two moderators: Jun Fan, senior hardware engineer at NCR, and Apple Computer's principal signal-integrity engineer, Zhiping Yang. Panelists include Bruce Archambeault, senior technical staff member at IBM; Nozad Karim, vice president at Amkor Technology; Northrop Grumman signal-integrity manager Eric Montgomery; Sun Microsystems' senior staff engineer Istvan Novak; Joel Peiffer, lead engineering specialist at 3M; and Hong Shi, lead electrical engineer in Altera's Packaging Technology Group.
