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An Engineer's Guide to DesignCon: Management panels

By Staff -- EDN, 2/6/2006

DesignCon 2006 will include several EDA and design-related management panels.

The business-panel track will kick off Tuesday morning with a panel entitled "Engineering in the United States." Moderated by Electronic News editor-in-chief Ed Sperling, the panel will examine how engineering education in the US stacks up against the growing education enterprises in other countries. It will also look at how US engineering education impacts the nation's ability to compete in a global marketplace and what effect reduced resources may have on Silicon Valley's position as the capital of high tech. Panelists include Silicon Valley Leadership Group's Carl Guardino, venture capitalist Jim Hogan, Intel Worldwide Higher Education Manager Timothy Saponas, and Belle W.Y. Wei, Dean of San Jose State University's College of Engineering.

If you're interested in whether or not the EDA industry is struggling, you may want to check out the Tuesday morning panel on "why the EDA industry is stagnating, or is it?" The panel will debate the state of EDA in today's exacting and demanding design world, discussing whether the design tools themselves are a hindrance to next-stage chip, package, and board design, or a vital technology enabling next-level design. Moderated by editor Richard Goering, the panel includes eSilicon CEO Jack Harding, venture capitalist Jim Hogan, Optimal Corp.Chairman Len Perham, Gartner Dataquest chief EDA analyst Gary Smith, and Richard Tobias, CTO at Pixelworks.

Tuesday afternoon will feature two EDA business panels. Venture Capitalist Lucio Lanza will moderate a panel on the cost of missing bugs in the IC design cycle. Panelists include MIPS CEO John Bourgoin; Benny Chang, Tundra Semiconductor's vice president of engineering; Robert Hum, general manager of Mentor Graphics' verification and test group; Jasper Design Automation CEO Kathryn Kranen; and IBM distinguished engineer Wolfgang Roesner.

The other Tuesday-afternoon panel will look at the emerging EDA niche, DFM (design for manufacturing). Editor Dylan McGrath moderates, with panelists Dinesh Bettadapur, CEO of ASML MaskTools; Franklin Kalk, CTO of Toppan Photomasks; Cadence Design Systems vice president Mark Miller; Applied Materials CTO Mike Smayling; Vincent Tong, vice president at Xilinx; and Hamid Torabi, CTO at IBM.

Tuesday afternoon will also feature two management panels, "IP Protection is Whose Problem?" and "Women in Design." The former will look at who is responsible for developing IP-protection standards, implementing those standards, and then enforcing adherence to IP rights. The panel will be moderated by Gartner Dataquestresearch director John Barber and will include panelists Joachim Kunkel, vice president of engineering IP at Synopsys; Open-Silicon co-founder and vice president Satya Gupta; LSI Logic CTO Gary Delp; and Denali co-founder and CTO Mark Gogolewski.

"Women in Design" will examine the rewards and unique challenges women face in choosing a design career. Moderated by Darlene Solomon, Agilent Technologies' vice president and director of Agilent Laboratories, the panel will include Jasper Design Automation CEO Kathryn Kranen; San Jose State University College of Engineering Dean Belle Wei; Kathy Werner, reuse manager at Freescale Semiconductor and chair of the VSI Quality Pillar; and Lisa Windover, project manager at Agilent Technologies' Agilent Laboratories.

Wednesday kicks off with two management panels. In the first, panelists will describe their experiences using an ESL (electronic system-level) methodology, discussingthe risks and associated costs of ESL adoption. They will share insights into the immediate benefits and longer-term gains, discuss the greatest hurdles, and debate the return on investment, or lack thereof.

The panel is moderated by Gartner Dataquest EDA analyst Daya Nadamuni. Panelists include Emulex principal engineer Terry Doherty; ESLX president Jack Donovan; Summit Design CEO Emil Girczyc; the director of Synopsys system-level solutions group, Rindert Schutten; Richard Tobias; and Vojin Zivojnovic, vice president of ESL tools at ARM.

If you're interested in jumping into the EDA business and are wondering about the ins and outs, ups and downs, and value of online electronic marketing, check out the second Wednesday morning business panel: "Make Technical On-Line Marketing Truly 'Technical' From Tactics to Strategy: What Works and What Doesn't?" Moderated by editor Ed Y. Zhang, the panel includes Forte Design Systems vice president Brett Cline; Gartner analyst Dean Freeman; Bluespec marketing vice president George Harper; GiDEL vice president Shlomo Keisari; eASIC senior corporate communications director Tsipi Landen; Calypto Design Systems vice president Michael Sanie; and Adam Traidman.

Wednesday afternoon features four management panels. "The Growing Cost of EDA Tools: When to Build versus Buy?" will be moderated by Gary Smith and will feature Brett Cline; Richard Tobias; Synopsys senior vice president of marketing Jay Greenberg; Zenasis president Dennis Harmon; and Scott Peterson Director of RapidChip Methodology at LSI Logic.

The second management panel appears to mislabeled, as panelists will look toward the technical as well as business challenges of 100G Ethernet.

The panel "The Need for 100G Ethernet?" is moderated by editor Loring Wirbel with panelists Adam Bechtel, director of global network architecture for Yahoo!; Lawrence Berkeley National Lab engineer Mike Bennett; Brad Booth, the director of advanced products at Quake Technologies; and Joel Goergen, chair of IEEE 802.3an and vice president of technology and chief scientist for Force10 Networks.

The third management panel is actually a business panel entitled "The Business of DFM: Critical Issues and Business Implications." Moderated by Canaccord Adams financial analyst Dennis Wassung Jr., the session includes SIGMA-C vice president ThomasBlaesi; Mentor Graphics' market development manager Jean-Marie Brunet; consultant Riko Radojcic; TSMC marketing director Edward Wan; Jim Wiley, senior technical director at Brion Technologies; and Yervant Zorian, vice president and chief scientist at Virage Logic.

Meanwhile, EDN's new executive editor, Ron Wilson, is moderating a panel on IP reuse in circuit-board design. Officially titled "Reference Design or IP: What are the Reuse Trends for High-Performance PCB Design?" the panel includes Vipul Badoni, senior manager of the high-speed IO Applications engineering group at Altera; Jerry Durand, CEO of Durand Interstellar; Randy Eager, CEO of DesignAdvance Systems; Farhad Haghighi, founder and CEO of TaraCom; John Isaac, director of market development for the systems design division at Mentor Graphics; and Cadence high-speed products group marketing director Hemant Shah.